Intel C2550 FH8065401488912 데이터 시트
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FH8065401488912
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
308
Order Number: 330061-002US
0
7:1
TGTADDR
Target Address
: 7-bit address field indicating the target SMBus/I
2
C
address.
Note:
See
for restrictions on writes to certain
addresses.
0
0
RW
Read/Write
: Set to 1 to indicate a Read Request. Cleared to 0 to indicate a
Write Request. Combinations of this bit and the WRLNTH, RDLNTH, and C/
WRL fields are decoded by the hardware to distinguish between various types
of SMBus cycles and I
2
C cycles.
Note:
For SMBus Process Call commands, this bit must always be cleared
to 0.
Note:
See
for restrictions on writes to certain
addresses.
1
31:24
TxBytes
Transmitted Bytes
: The hardware updates this field to indicate how many
bytes transmitted by it were ACKed by the target. This field provides the
firmware the ability to reconstruct which particular byte was NACKed by
target.
This count is 1-based and includes all the bytes sent by the hardware which
This count is 1-based and includes all the bytes sent by the hardware which
are ACKed by target including address.
Value of 0 means address phase NACKed or collision on address phase.
Value of 0 means address phase NACKed or collision on address phase.
1
23:16
RXBytes
Received Bytes
: The hardware indicates how many bytes of received data it
is writing to memory (into the data buffer). The count is 1-based, i.e., the
value 0h means 0 bytes of data. The hardware limitation is for a 240-bytes
data buffer implying that for a maximum SMBus legal block read of 32 bytes
with the PEC, it forwards to memory the 240 bytes of data; the byte count
received.
Note:
PEC is not forwarded to the firmware, since the firmware explicitly
enables/disables PEC per master transaction. The hardware returns
the PEC check in the CRC field, which the firmware inspects.
1
15
Reserved
Reserved
1
14:12
COLRTRY
Collision Retry
: The hardware indicates the number of collisions on the last
attempt before retiring the descriptor.
1
11:8
RETRY
Retry Count
: The hardware indicates the count with the number of retries
attempted before retiring the descriptor.
1
7
LPR
Large Packet Received
: The hardware sets this bit to indicate that more
data was sent by the target than expected by the firmware and exceeds the
allocated receive data space (TRxCTRL.MRxB).
The hardware must DMA the data to the buffer in memory in the space
The hardware must DMA the data to the buffer in memory in the space
allocated, dropping the extra bytes.
1
6
COL
Collisions
: Set to 1 by the hardware to indicate that failure was due to
number of collisions exceeding the collision retry count (RPOLICY.COLRTRY).
1
5
CLTO
Clock Low Time Out
: Set to 1 by the hardware to indicate unexpected
time-out seen on the bus during the course of the request.
This bit being set indicates that SMB clock signal was held low by external
This bit being set indicates that SMB clock signal was held low by external
device for the count as programmed in CNT.
1
4
CRC
CRC Error:
Set to 1 by the hardware to indicate CRC error
1
on the request.
For read requests with PEC, the hardware sets this bit if the PEC received
from target does not match PEC calculated by the hardware.
For write Requests with PEC, the hardware sets this bit if the target NACKs
For write Requests with PEC, the hardware sets this bit if the target NACKs
the PEC byte.
1
3
NAK
NACK Received:
Set to 1 by the hardware to indicate unexpected NACK
asserted by target.
1
2:0
Reserved
Reserved
1
0
SCS
Success
: Set to 1 by the hardware to indicate that cycle was transferred
successfully. 0 indicates that some error was encountered and other bits in
the status indicate the error.
Table 15-13. Master Descriptor Field Descriptions (Sheet 2 of 3)
Dword #
Bit
#
Field
Description