Intel C2550 FH8065401488912 데이터 시트
제품 코드
FH8065401488912
Volume 3—Signal Electrical and Timing Characteristics—C2000 Product Family
2.5 and 1 Gigabit Ethernet (GbE) Interface
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 3 of 3
September 2014
650
Order Number: 330061-002US
33.3.3.1.5
Transition Time
The rising edge transition time is recommended to be between 60 ps and 130 ps as
measured at the 20% and 80% levels of the peak-to-peak differential value of the
waveform using the high-frequency test pattern of 48A.1 in Annex 48A - Jitter Test
Patterns of IEEE Standard 802.3*-2008. The falling edge transition time is
recommended to be between 60 ps and 130 ps as measured at the 80% and 20%
levels of the peak-to-peak differential value of the waveform using the high-frequency
test pattern of 48A.1.
33.3.3.1.6
Transmit Jitter
The transmitter shall have a maximum total jitter of 0.350 UI peak-to-peak, a
maximum deterministic component of 0.170 UI peak-to-peak, and a maximum random
component of 0.270 UI peak-to-peak. Jitter specifications include all but 10–12 of the
jitter population. Transmit jitter test requirements are specified in
33.3.3.1.7
Transmit Jitter Test Requirements
Transmit jitter is defined with respect to the transmitter differential output signal at
TP1, as shown in
, and the test
procedure resulting in a BER bathtub curve such as that described in Annex 48B - Jitter
Test Methods of IEEE Standard 802.3*-2008. For the purpose of jitter measurement,
the effect of a single-pole high-pass filter with a 3 dB point at 1.875 MHz is applied to
the jitter. The data pattern for jitter measurements shall be the jitter tolerance test
pattern defined in Annex 48A.5. For this test, all other transmitters shall be active and
terminated with a load meeting the requirements described in
. Crossing times are defined with respect to the mid-point (0 V)
of the AC-coupled differential signal.