Intel C2350 FH8065401488914 데이터 시트

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 3 of 3

September 2014

636

Order Number: 330061-002US

T

SU

 + T

HD

170

ps

4

T

DQS_CO

-125

125

ps

T

WPRE

1.00

TCK

T

WPST

0.30

0.50

TCK

1.

The CMD time is measured w.r.t. differential crossing of CK and CKB. The tCMDVB and tCMDVA are adjusted for proper 

CMD setup and hold time requirement at DRAM. The command timing assumes CMD-1N mode.

2.

The CTL time is measured w.r.t. differential crossing of CK and CKB. The tCTLVB and tCTLVA are adjusted for proper CTL 

setup and hold time requirement at DRAM.

3.

The accurate strobe placement using write training algorithm is performed which guarantees the required data setup/

hold time w.r.t. strobe differential crossing at the DRAM input.

4.

The read training algorithm places the DQS internally inside the DDR interface to have equal tSU and tHD timings.

5.

All the timing windows are measured at 50% of the respective DDR signal swing.