Intel E3845 FH8065301487715 데이터 시트
제품 코드
FH8065301487715
SIO - I
2
C Interface
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
3821
However, according to the I
2
C specification, standard mode devices are not upward
compatible and should not be incorporated in a fast-mode I
2
C bus system since they
cannot follow the higher transfer rate and unpredictable states would occur.
26.2.3
Functional Description
•
The I
2
C master is responsible for generating the clock and controlling the transfer
of data.
•
The slave is responsible for either transmitting or receiving data to/from the
master.
master.
•
The acknowledgement of data is sent by the device that is receiving data, which
can be either a master or a slave.
can be either a master or a slave.
•
Each slave has a unique address that is determined by the system designer:
— When a master wants to communicate with a slave, the master transmits a
START/RESTART condition that is then followed by the slave's address and a
control bit (R/W), to determine if the master wants to transmit data or receive
data from the slave.
control bit (R/W), to determine if the master wants to transmit data or receive
data from the slave.
— The slave then sends an acknowledge (ACK) pulse after the address.
•
If the master (master-transmitter) is writing to the slave (slave-receiver)
— The receiver gets one byte of data.
— This transaction continues until the master terminates the transmission with a
STOP condition.
•
If the master is reading from a slave (master-receiver)
— The slave transmits (slave-transmitter) a byte of data to the master, and the
master then acknowledges the transaction with the ACK pulse.
— This transaction continues until the master terminates the transmission by not
acknowledging (NACK) the transaction after the last byte is received, and then
the master issues a STOP condition or addresses another slave after issuing a
RESTART condition. This behavior is illustrated in below figure.
the master issues a STOP condition or addresses another slave after issuing a
RESTART condition. This behavior is illustrated in below figure.
Figure 120.Data Transfer on the I
2
C Bus
D a t a
C l o c k
S T A R T o r
R E S T A R T
C o n d i t i o n s
C o n d i t i o n s
S
o r
R
M S B
L S B
A C K
f r o m s l a v e
B y t e C o m p l e t e
I n t e r r u p t w i t h i n
I n t e r r u p t w i t h i n
S l a v e
C l o c k h e l d l o w
w h i l e s e r v i c i n g
i n t e r r u p t s
S T O P A N D
R E S T A R T
C o n d i t i o n s
C o n d i t i o n s
P o r R
R o r P
1
2
3 - 8
7
8
9
1
2
9
f r o m r e c e i v e r
A C K