Intel E3845 FH8065301487715 데이터 시트
제품 코드
FH8065301487715
PCU – Intel
®
Legacy Block (iLB) Overview
Intel
®
Atom™ Processor E3800 Product Family
4480
Datasheet
— Three timers and one counter
— Memory mapped registers
•
Real-Time Clock (RTC)
— 242 byte RAM backed by battery (aka CMOS RAM)
— Can generate wake/interrupt when time matches programmed value
— I/O and indexed registers
34.2.2
Non-Maskable Interrupt
NMI support is enabled by setting the NMI Enable (NMI_EN) bit, at IO Port 70h, Bit 7,
to 0b.
to 0b.
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
§
Table 318. NMI Sources
NMI Source
NMI Source
Enabler/
Disabler
NMI Source
Status
Alternate
Configuration
SERR# goes active
NOTE: A SERR# is only generated
NOTE: A SERR# is only generated
internally in the SoC)
NSC.SNE
NSC.SNS
All NMI sources may,
alternatively, generate a
SMI by setting
GNMI.NMI2SMIEN=1b
alternatively, generate a
SMI by setting
GNMI.NMI2SMIEN=1b
The SoC uses
GNMI.NMI2SMIST for
observing SMI status
GNMI.NMI2SMIST for
observing SMI status
IOCHK# goes active
NOTE: A IOCHK# is only generated
NOTE: A IOCHK# is only generated
as a SERIRQ# frame
NSC.INE
NSC.INS
ILB_NMI goes active
NOTE: Active can be defined as
NOTE: Active can be defined as
being on the positive or
negative edge of the signal
using the GNMI.GNMIED
register bit.
negative edge of the signal
using the GNMI.GNMIED
register bit.
GNMI.GNMIED GNMI.GNMIS
Software sets the GNMI.NMIN
register bit
register bit
GNMI.NMIN
GNMI.NMINS