Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

3041

The starting destination address is programmed by software before the DMA channel is 

enabled, or by an LLI update before the start of the DMA transfer. While the DMA 

transfer is in progress, this register is updated to reflect the destination address of the 

current transfer.

Default: 00000000h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SA

R

31:0

0h

RW

Current Source Address of DMA transfer. Updated after each source transfer. The 

SINC field in the CTL_LO[n]: Control Register determines whether the address 

increments or is left unchanged on every source transfer throughout the block transfer. 

When the channel is enabled (i.e. CH_EN is 1), the read back value will reflect the 

updated source transfer addresses. However, when the channel is disabled, the original 

programmed value will be reflected when reading this register. It's important to notice 

the following: 1. Once the block transfer is in progress (i.e. when channel is enabled), 

the read-back value correlates with the OCP Read Address that one would see in an OCP 

tracker. 2. If the read to this register comes during a block transfer, the LAST DMA Read 

address sent on the OCP before the register read is what's reflected in the read-back 

value. 3. If the last DMA read was a burst read (i.e. burst length ) 1), the read-back 

value reflects the first address of the burst read since this is what gets sent on the OCP 

fabric. 4. If the read to the register occurred after the whole block got transferred, then 

the channel gets disabled and the returned value would be the original programmed 

value. 5. Since the read-back value is OCP based, only DW aligned addresses will be 

reflected (i.e. OCP Byte-Enable values would not be reflected) 6. Based on the above 

remarks, this value should be used as pseudo DMA read progress indicator when the 

channel is enabled and not an absolute one. Decrementing addresses are not supported

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:21, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DAR