Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

3805

21

0b

RW

Transmit Service Request Enable (TSRE): 
•

0 = DMA Service Request is disabled 

•

1 = DMA Service Request is enabled 

20

0b

RW

Receive Service Request Enable (RSRE): 
•

0 = DMA Service Request is disabled 

•

1 = DMA Service Request is enabled 

19

0b

RW

Receiver Time-out Interrupt Enable (TINTE): 
•

0 = Receiver Time-out interrupts are disabled 

•

1 = Receiver Time-out interrupts are enabled 

18

0b

RW

Peripheral Trailing Byte Interrupts Enable (PINTE): 
•

0 = Peripheral Trailing Byte Interrupts are disabled 

•

1 = Peripheral Trailing Byte Interrupts are enabled 

17

0b

RW

Reserved

16

0b

RW

Invert Frame Signal (IFS): 
•

0 = Frame polarity is determined by SSP format and PSP polarity bits. 

•

1 = Frame signal will be inverted from the normal SSP frame signal (as defined by 

the SSP format and PSP polarity bits). 

15

0b

RW

Select FIFO for EFWR (test mode bit) (when EFWR=1) 

•

0 = Transmit FIFO is selected for both writes and reads through the SSP Data 

Register (SSDR) 

•

1 = Receive FIFO is selected for both writes and reads through the SSP Data 

Register (SSDR) 

14

0b

RW

Test mode bit. 

•

0 = FIFO write/read special function is disabled (normal SSP operational mode) 

•

1 = FIFO write/read special function is enabled 

13:10

0000b

RW

Sets threshold level at which receive FIFO 

asserts interrupt. This level should be set to the desired threshold value minus 1.

9:6

0000b

RW

Sets threshold level at which transmit FIFO 

asserts interrupt. This level should be set to the desired threshold value minus 1.

5

0b

RW

Microwire Transmit Data Size (MWDS): 
•

0 = 8-bit command words are transmitted 

•

1 = 16-bit command words are transmitted 

4

0b

RW

Motorola SPI SSPSCLK Phase Setting (SPH): 
•

0 = SSPSCLK is inactive one cycle at the start of a frame and cycle at the end of a 

frame 

•

1 = SSPSCLK is inactive cycle at the start of a frame and one cycle at the end of a 

frame 

3

0b

RW

Motorola SPI SSPSCLK Polarity Setting (SPO): 
•

0 = The inactive or idle state of SSPSCLK is low 

•

1 = The inactive or idle state of SSPSCLK is high 

2

0b

RW

Test mode bit. 

•

0 = Normal serial port operation enabled 

•

1 = Output of transmit serial shifter connected to input of receive serial shifter, 

internally 

1

0b

RW

Transmit FIFO Interrupt Enable (TIE): 
•

0 = Transmit FIFO level interrupt is disabled 

•

1 = Transmit FIFO level interrupt is enabled