Intel E3815 FH8065301567411 데이터 시트

Intel

®

 Atom™ Processor E3800 Product Family

4314

Datasheet

This register contains misc. fields used to record events pertaining to SOC power 

management. Unless otherwise indicated, all RWC bits are cleared with a write of 1 by 

software.

Default: 00000000h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

re

se

rv

ed

sp

s

no

_reb

oot

sx

_

ent_to

_

en

re

se

rv

ed

2

timing_t581

31:6

0b

RO

Reserved.

5

0b

RW

When cleared (default) the SOC will drive 

INIT# in response to the shutdown Message. When set to 1, SOC will treat the 

shutdown message similar to receiving a CF9h I/O write, and will drive PMU_PLTRST 

active. . BIOS guide note: This register is reset any time PMU_PLTRST asserts.

4

0b

RW

This bit is set when the No Reboot strap is 

sampled high on COREPWROK. This bit may be set or cleared by software if the strap is 

sampled low but may not override the strap when it indicates No Reboot. When set, the 

TCO timer will count down and generate the SMI# on the first timeout, but will not 

reboot on the second timeout.

3

0b

RW

This policy 

bit determines whether the SOC will apply a timeout to the S1/S3/S4/S5 entry flow. If 

this timeout is enabled and the entry flow appears to be hung, the SOC will trigger a 

straight-to-S5 global reset. Encodings: 0: Timeout disabled (default) 1: Timeout 

enabled reset_type=RSMRST_B

2

0b

RO

Reserved.

1:0

0b

RW

This field configures the t581 timing 

involved in the power down flow (CPU Power Good indication inactive to PLL Enable 

inactive). Encodings (all min timings): 00: 10 us (default) 01: 100 us 10: 1 ms 11: 10 

ms reset_type=Resume Well Reset#

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 

32 bits)
PMC_BASE_ADDRESS Reference: 

[B:0, D:31, F:0] + 44h