Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

4475

All bits in this register are implemented in a slow (64khz) clock domain. Therefore, 

software must poll the register until a write takes effect before assuming that a write 

has completed internally. Also, software must confirm the prior written value before 

writing to the register again.

Default: 00h

7:1

0000000b

RO

Reserved

0

0b

RW

HOST_NOTIFY_STS: The SMBus controller sets this bit to a 1 when it has 

completely received a successful Host Notify Command on the SMBus pins. Software 

reads this bit to determine that the source of the interrupt or SMI# was the reception of 

the Host Notify Command. Software clears this bit after reading any information needed 

from the Notify address and data registers by writing a 1 to this bit. Note that the 

SMBus controller will allow the Notify Address and Data registers to be over-written 

once this bit has been cleared. When this bit is 1, the SMBus controller will NACK the 

first byte (host address) of any new 'Host Notify' commands on the SMBus. Writing a 0 

to this bit has no effect.

I/O Register

(Size: 8 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:31, F:3] + 20h

7

4

0

0

0

0

0

0

0

0

0

RSV

1

SMBAL

T

DIS

HNW

A

K

E

EN

HN

IN

TRE

N

7:3

00000b

RO

Reserved

2

0b

RW

Software sets this bit to 1 to block the generation of the interrupt or 

SMI# due to the SMB_ALERTB source. This bit is logically inverted and 'AND'ed with the 

SMB_ALERTB bit of HSTS register. The resulting signal is distributed to the SMI# and/or 

interrupt generation logic.

1

0b

RW

Software sets this bit to 1 to enable the reception of a Host Notify 

command as a wake event.

0

0b

RW

Software sets this bit to 1 to enable the generation of interrupt or SMI 

when HOST_NOTIFY_STS is 1. This enable does not affect the setting of the 

HOST_NOTIFY_STS bit. When the interrupt is generated, either INTRB or SMI is 

generated, depending on the value of the SMI_EN bit (D31, F3, Off40h, B1). If the 

HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI) 

will be generated. The interrupt (or SMI) is logically generated by AND'ing the STS and 

INTREN bits.