Intel E3815 FH8065301567411 데이터 시트

Intel

®

 Atom™ Processor E3800 Product Family

5292

Datasheet

The processor generates an interrupt acknowledge cycle that is translated into a 
Interrupt Acknowledge Cycle to the SoC. The PIC translates this command into two 
internal INTA# pulses expected by the 8259 controllers. The PIC uses the first internal 
INTA# pulse to freeze the state of the interrupts for priority resolution. On the second 
INTA# pulse, the master or slave sends the interrupt vector to the processor with the 
acknowledged interrupt code. This code is based upon the ICW2.IVBA bits, combined 
with the ICW2.IRL bits representing the interrupt within that controller.

References to ICWx and OCWx registers are relevant to both the master and slave 
8259 controllers.

1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or 

seen high in level mode, setting the corresponding IRR bit.

2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.

3. The processor acknowledges the INTR and responds with an interrupt acknowledge 

cycle.

IRR

Interrupt Request Register. This bit is set on a low to high transition of the interrupt 
line in edge mode, and by an active high level in level mode.

ISR

Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, 
when an interrupt acknowledge cycle is seen, and the vector returned is for that 
interrupt.

IMR

Interrupt Mask Register. This bit determines whether an interrupt is masked. 
Masked interrupts will not generate INTR.

IRQ7,15

ICW2.IVBA

111

IRQ6,14

110

IRQ5,13

101

IRQ4,12

100

IRQ3,11

011

IRQ2,10

010

IRQ1,9

001

IRQ0,8

000