Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
Intel
®
Atom™ Processor E3800 Product Family
5296
Datasheet
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
The Poll command is issued by setting OCW3.PMC. The PIC treats its next I/O read as
an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads
the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte
returned during the I/O read contains a 1 in Bit 7 if there is an interrupt, and the binary
code of the highest priority level in Bits 2:0.
an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads
the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte
returned during the I/O read contains a 1 in Bit 7 if there is an interrupt, and the binary
code of the highest priority level in Bits 2:0.
42.1.4.6
Edge and Level Triggered Mode
In ISA systems this mode is programmed using ICW1.LTIM, which sets level or edge for
the entire controller. In the SoC, this bit is disabled and a register for edge and level
triggered mode selection, per interrupt input, is included. This is the Edge/Level control
Registers ELCR1 and ELCR2.
the entire controller. In the SoC, this bit is disabled and a register for edge and level
triggered mode selection, per interrupt input, is included. This is the Edge/Level control
Registers ELCR1 and ELCR2.
If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
42.1.5
End of Interrupt (EOI) Operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC
before returning from a service routine, the EOI command; or automatically when the
ICW4.AEOI bit is set to 1.
before returning from a service routine, the EOI command; or automatically when the
ICW4.AEOI bit is set to 1.
42.1.5.1
Normal End of Interrupt
In normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears
the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of
operation of the PIC within the SoC, as the interrupt being serviced currently is the
interrupt entered with the interrupt acknowledge. When the PIC is operated in modes
that preserve the fully nested structure, software can determine which ISR bit to clear
by issuing a Specific EOI.
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears
the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of
operation of the PIC within the SoC, as the interrupt being serviced currently is the
interrupt entered with the interrupt acknowledge. When the PIC is operated in modes
that preserve the fully nested structure, software can determine which ISR bit to clear
by issuing a Specific EOI.
An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is in the special
mask mode. An EOI command must be issued for both the master and slave controller.
mask mode. An EOI command must be issued for both the master and slave controller.