Intel E3815 FH8065301567411 데이터 시트

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

5303

Master Operational Control Word 1 (Interrupt Mask)

Default: 00h

Slave Initialization Command Word 1.A write to Initialization Command Word 1 starts 

the interrupt controller initialization sequence, during which the following occurs: * The 

Interrupt Mask register is cleared. * IRQ7 input is assigned priority 7. * The slave mode 

address is set to 7. * Special Mask Mode is cleared and Status Read is set to IRR. Once 

this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete 

the initialization sequence.

Default: 00h

3

0b

WO

Buffered Mode (BUF): Must be cleared for non-buffered mode. Writing 1 will result 

in undefined behavior.

2

0b

WO

Master/Slave in Buffered Mode (MSBM): Not used. Should always be 

programmed to 0.

1

0b

WO

Automatic End of Interrupt (AEOI): This bit should normally be programmed to 

0. This is the normal end of interrupt. If this bit is 1, the automatic end of interrupt 

mode is programmed.

0

1b

WO

Microprocessor Mode (MM): This bit must be written to 1 to indicate that the 

controller is operating in an Intel Architecture-based system. Writing 0 will result in 

undefined behavior.

I/O Register

(Size: 8 bits)

7

4

0

0

0

0

0

0

0

0

0

IRM

7:0

00h

RW

Interrupt Request Mask (IRM): When a 1 is written to any bit in this register, the 

corresponding IRQ line is masked. When a 0 is written to any bit in this register, the 

corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by 

the controller. Masking IRQ2 on the master controller will also mask the interrupt 

requests from the slave controller.

I/O Register

(Size: 8 bits)