Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2038
Datasheet
25
0h
RW
i_rxsq_asyncmode_h:
Squelch Async Startup Mode This squelch startup mode is
power state independent. When enabled, the squelchen signal sent to Modphy will
asynchronously enable the squelch detector circuit. Once enabled, the squelch detector
circuit will asynchronously send an unfiltered/unqualified squelch indication signal out
of Modphy. The squelch indication signal will initially be unstable, so it is up to the
consumer of this signal to filter/qualfiy it accordingly. The asynchronous squelch startup
mode is beneficial because it significantly reduces the squelch startup latency. This
decrease in latency does come at the cost of slightly higher power when squelch is not
enabled as the IREF and Squelch Keeper circuits must remain enabled. When disabled,
the squelch startup sequence is synchronous in nature and the squelch indication signal
sent out of Modphy is stable/filtered.
24
1h
RW
i_rxsquelchstby_h:
Fast Squelch Enable Mode Bit to keep the IREF (ivrefen) on
during P2 and reduce squelch startup time.
23:18
0h
RW
reserved519:
reserved
17:16
0h
RW
cri_dfx_evenoddmask_1_0:
Pattern Checker Even/Odd Bit Error Mask Select 00 : no
masking; all errors will be counted 01: select odd path, mask even path; only errors on
bits [1,3,5,7,9] are counted 10: select even path, mask odd path; only errors on bits
[0,2,4,6,8] are counted 11: reserved;
15:12
0h
RW
reserved518:
reserved
11:10
0h
RW
cri_dfx_lce2patsrc_1_0:
Local Compare Engine 2 Pattern Source In a lane with two
Tx paths, this selects between using Pattern Buffer or PRBS as source of LCE patterns
for the second LCE. The DFXLCEPATSRC selects for the first LCE. 0 : Pattern Buffer
(default) 1 : PRBS
9:8
0h
RW
cri_dfx_lcepatsrc_1_0:
Local Compare Engine Pattern Source. Selects between using
Pattern Buffer or PRBS as source of LCE patterns. 00 : Pattern Buffer; use LCE default
training pattern; 01: Pattern Buffer; use the first 40b of pattern buffer for training. 10:
PRBS; use LCE default training pattern; 11: PRBS; use the first 40b of pattern buffer for
training.
7:6
0h
RW
reserved517:
reserved
5:4
0h
RW
txloadgen_ctr_val:
TxLoadGen Pulse Width Control Controls the pulse width of
txloadgenen from PCS to Tx upar. This is used in MAC inititated digital far end loopback
mode in PCIE family. 00 - txloadgenen pulse width is 4 symbol clocks (default) 01-
txloadgenen pulse width is 2 symbol clocks 10 - txloadgenen pulse not generated 11 -
txloadgenen pulse width is 6 symbol clocks
3
0h
RW
cri_txhighpowerei_ovrden:
TxHighPowerEI Override Mode Enable 0 - TxHighPowerEI
to TxuPAR driven by Logic 1 - TxHighPowerEI to TxuPAR driven by override register
value(s).
2
0h
RW
cri_tx1highpowerei_ovrdval:
Tx1HighPowerEI Override Value Valid when
cri_txhighpowerei_ovrden = 1'b1. 0 - Tx1HighPowerEI disabled 1 - Tx1HighPowerEI
enabled
1
0h
RW
cri_tx2highpowerei_ovrdval:
Tx2HighPowerEI Override Value Valid when
cri_txhighpowerei_ovrden = 1'b1. 0 - Tx2HighPowerEI disabled 1 - Tx2HighPowerEI
enabled
0
1h
RW
p2_fast_exit_en:
P2 Fast Exit Mode Enable Common Mode sustainer will be enabled
during P2 when this bit is asserted. 1: P2 Fast Exit Mode Enable 0: P2 Fast Exit Mode
Disable
Bit
Range
Default &
Access
Description