Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
614
Datasheet
14.10.182 PIPEAWIDEGAMUTCOLORCORRECTIONC01_C00COEFFICIENTS
—Offset 600B0h
When color correction matrix enable bit is set in PIPEACONF register, each of pixels in
the pipe is multiplied with this matrix. Color matrix is used to convert pixels from one
RGB color space to another RGB color space. There are many applications for the use of
this matrix like gamut mapping between 72 percent color gamut to 92 percent color
gamut. Each coefficient is a 12-bit signed fixed-point number. The application of
coefficients are as follows:
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0b
RW
SDP_SEND_FREQUENCY:
00: off, not sending
01: send one every frame
10: send once
11: reserved
Programming note: This field shall be programmed either send once or send one every
frame when SW driver sets PSR active entry bit. When PSR is enabling this field is
ignored. One SDP is sent in every frame until source is in PSR active state
29:16
0b
RW
RESERVED:
Reserved.
15:8
0b
RW
DB1:
: Programmed by display driver in manual mode, auto-generate by display
controller in all other modes
7:0
0b
RW
DB0:
: Bits 7:4: Stereo Interface Method Specific ParameterBits 3:0: Stereo Interface
Method Code.
This field is programmed by display driver for stereo display configuration
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESE
RVE
D
C
01_COE
FFIC
IE
N
T
RES
E
RVE
D
_1
C
00_COE
FFIC
IE
N
T
Bit
Range
Default &
Access
Field Name (ID): Description
31:28
0b
RW
RESERVED:
Reserved.
27:16
0b
RW
C01_COEFFICIENT:
12-bit 2 s complement signed value that is programmed for linea.
The range of the value can be from -1.999 to +1.999.
15:12
0b
RW
RESERVED_1:
Reserved.