Intel N2820 FH8065301616603 데이터 시트
제품 코드
FH8065301616603
Datasheet
979
PCU – Power Management Controller (PMC)
PMC_CORE_PWROK
I
CMOS
Core Power OK: When asserted, this signal is an indication
to the processor that all of its core power rails have been
stable for 10 ms. It can be driven asynchronously. When it is
negated, the processor asserts PMC_PLTRST#.
NOTE: It is required that the power rails associated with PCI
Express (typically the 3.3V, 5V, and 12V core well
rails) have been valid for 99 ms prior to
PMC_CORE_PWROK assertion in order to comply with
the 100 ms T
PVPERL
PCI Express 2.0 specification on
PMC_PLTRST# deassertion.
NOTE: PMC_CORE_PWROK must not glitch, even if
PMC_RSMRST# is low.
PMC_PLTRST#
O
CMOS
Platform Reset: The processor asserts this signal to reset
devices on the platform. The processor asserts the signal
during power-up and when software initiates a hard reset
sequence through the Reset Control (RST_CNT) register.
PMC_PWRBTN#
I
CMOS
Power Button: The signal will cause SMI# or SCI to indicate
a system request to go to a sleep state. If the system is
already in a sleep state, this signal will cause a wake event. If
the signal is pressed for more than 4 seconds, this will cause
an unconditional transition (power button override) to the S5
state. Override will occur even if the system is in the S3 & S4
states. This signal has an internal pull-up resistor and has an
internal ~16 ms de-bounce on the input.
PMC_RSMRST#
I
CMOS
Resume Well Reset: Used for resetting the resume well. An
external RC circuit is required to guarantee that the resume
well power is valid prior to this signal going high.
PMC_RSTBTN#
I
CMOS
System Reset: This signal forces an internal reset after being
debounced (~16 ms).
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PMC_SLP_S3#
O
CMOS
S3 Sleep Control: This signal is for power plane control. It
can be used to control system power when it is in a S3
(Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off)
states.
PMC_SLP_S4#
O
CMOS
S4 Sleep Control: This signal is for power plane control. It
can be used to control system power when it is in a S4
(Suspend to Disk) or S5 (Soft Off) state.
PMC_SUS_STAT#
O
CMOS
Suspend Status: This signal is asserted by the processor to
indicate that the system will be entering a low power state
soon. This can be monitored by devices with memory that
need to switch from normal refresh to suspend refresh mode.
It can also be used by other peripherals as an indication that
they should isolate their outputs that may be going to
powered-off planes.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PMC_SUSCLK
O
CMOS
Suspend Clock: This 32 kHz clock is an output of the RTC
generator circuit for use by other chips for refresh clock.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PMC_SUSPWRDNACK
O
CMOS
Suspend Power Down Acknowledge: Asserted by the
processor when it does not require its Suspend well to be
powered. This pin requires a pull-up to UNCORE_V1P8_G3.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PMC_WAKE_PCIE[0]#
I
CMOS
PCI Express* Port 0 Wake Event: Sideband wake signal on
PCI Express asserted by a component requesting wake up.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
PMC_WAKE_PCIE[1]#
I
CMOS
PCI Express* Port 1 Wake Event: Sideband wake signal on
PCI Express asserted by a component requesting wake up.
This signal is multiplexed and may be used by other functions.
This signal is multiplexed and may be used by other functions.
Table 144. PMC Signals (Sheet 2 of 3)
Signal Name
Direction/
Type
Description