Motorola Espresso Maker MC68340 사용자 설명서

6- 22

MOTOROLA

. .

. .

.

NOTE
     1.  To cause another DMA transfer, the DREQx is asserted after DACKx is asserted and before DACKx is negated.
     2.  DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.

A31–A0

FC3–FC0

SIZ1–SIZ0

R/W

AS

DS

DSACKx

S0

S2

S4

S0

S0

S0

S4

D15–D0

DREQx

DACKx

DONEx

(OUTPUT)

DMA READ

CPU CYCLE

CLKOUT

CPU CYCLE

DMA WRITE

DMA READ

DMA WRITE

S0

S4

S4

S0

S0

S4

S4

S2

The following paragraphs contain a detailed description of each register and its specific
function. Figure 6-15 is a programmer's model (register map) of all registers in the DMA
module. Each channel has an independent set of registers. For more information about a
particular register, refer to the individual register description. The ADDRESS column
indicates the offset of the register from the base address of the DMA channel. The FC
column designation of S indicates that register access is restricted to supervisor only. A
designation of S/U indicates that access is governed by the SUPV bit in the module
configuration register (MCR).

Unimplemented memory locations return logic zero when accessed. All registers support
both byte and word transfers.

F

re

e

sc

a

le

 S

e

m

ic

o

n

d

u

c

to

r,

 I

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

  

 

Freescale Semiconductor, Inc.

For More Information On This Product,

   Go to: www.freescale.com

n

c

.

..