Xilinx DS610 사용자 설명서
DS610 July 16, 2007
1
Product Specification
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
Module 1:
•
Introduction
•
Features
•
Architectural Overview
•
Configuration Overview
•
General I/O Capabilities
•
Supported Packages and Package Marking
•
Ordering Information
Module 2:
The functionality of the Spartan™-3A DSP FPGA family is
described in the following documents.
described in the following documents.
•
Spartan-3 Generation FPGA User Guide
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Clocking Resources
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Digital Clock Managers (DCMs)
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Block RAM
-
Configurable Logic Blocks (CLBs)
·
·
Distributed RAM
·
SRL16 Shift Registers
·
Carry and Arithmetic Logic
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I/O Resources
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Programmable Interconnect
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ISE
TM
Software Design Tools and IP Cores
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Embedded Processing and Control Solutions
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Pin Types and Package Overview
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Package Drawings
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Powering FPGAs
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Power Management
•
XtremeDSP™ DSP48A for Spartan-3A DSP FPGAs
User Guide
-
-
DSP48A Slice Design Considerations
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DSP48A Architecture Highlights
·
·
18 x 18-Bit Multipliers
·
48-Bit Accumulator
·
18-bit Pre-Adder
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DSP48A Application Examples
•
Spartan-3 Generation Configuration User Guide
-
Configuration Overview
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Configuration Pins and Behavior
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Bitstream Sizes
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Detailed Descriptions by Mode
·
·
Master Serial Mode using Platform Flash PROM
·
Master SPI Mode using Commodity Serial Flash
·
Master BPI Mode using Commodity Parallel Flash
·
Slave Parallel (SelectMAP) using a Processor
·
Slave Serial using a Processor
·
JTAG Mode
-
ISE iMPACT Programming Examples
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MultiBoot Reconfiguration
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Design Authentication using Device DNA
Module 3:
•
DC Electrical Characteristics
-
-
Absolute Maximum Ratings
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Supply Voltage Specifications
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Recommended Operating Conditions
•
Switching Characteristics
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I/O Timing
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Configurable Logic Block (CLB) Timing
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Digital Clock Manager (DCM) Timing
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Block RAM Timing
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XtremeDSP Slice Timing
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Configuration and JTAG Timing
Module 4:
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Pin Descriptions
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Package Overview
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Pinout Tables
•
Footprint Diagrams
0
Spartan-3A DSP FPGA Family:
Data Sheet
Data Sheet
DS610 July 16, 2007
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0
Product Specification
R
SPARTAN-3A DSP
SPARTAN-3A DSP