Texas Instruments TMS3320C5515 사용자 설명서
0001 0000h
64K Minus 192 Bytes
DARAM
(D)
0009 0000h
SARAM
256K Bytes
External-CS2 Space
(C)
0200 0000h
0300 0000h
0400 0000h
0500 0000h
050E 0000h
128K Bytes Asynchronous (if MPNMC=1)
128K Bytes ROM (if MPNMC=0)
128K Bytes ROM (if MPNMC=0)
External-CS3 Space
(C)
External-CS4 Space
(C)
External-CS5 Space
(C)
BLOCK SIZE
DMA/USB/LCD
BYTE ADDRESS
(A)
ROM
(if MPNMC=0)
External-CS5
f MPNMC=1)
(C)
Space
(i
1M Minus 128K Bytes Asynchronous
1M Bytes Asynchronous
2M Bytes Asynchronous
4M Bytes Asynchronous
MEMORY BLOCKS
0001 00C0h
MMR (Reserved)
(B)
0100 0000h
External-CS0 Space
(C)(E)
8M Minus 320K Bytes SDRAM/mSDRAM
050F FFFFh
000000h
010000h
800000h
C00000h
E00000h
F00000h
FE0000h
CPU BYTE
ADDRESS
(A)
0000C0h
050000h
FFFFFFh
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System Memory
Figure 1-2. DSP Memory Map
A
Address shown represents the first byte address in each block.
B
The first 192 bytes are reserved for memory-mapped registers (MMRs).
C
Out of the four DMA controllers, only DMA controller 3 has access to the external memory space.
D
The USB controller does not have access to DARAM.
E
The CS0 space can be accessed by CS0 only or by CS0 and CS1.
1.2.1.1
On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the CPU byte address range 00 00C0h - 00 FFFFh and is composed of eight
blocks of 4K words each (see
blocks of 4K words each (see
). Each DARAM block can perform two accesses per cycle (two
reads, two writes, or a read and a write). DARAM can be accessed by the internal program, data, and
DMA buses.
DMA buses.
As shown in
, the DMA controllers access DARAM at an address offset 0x0001_0000 from the
CPU memory byte address space.
Table 1-2. DARAM Blocks
Memory Block
CPU Byte Address Range
DMA/USB Controller Byte Address Range
DARAM 0
(1)
00 00C0h - 00 1FFFh
0001 00C0h - 0001 1FFFh
DARAM 1
00 2000h - 00 3FFFh
0001 2000h - 0001 3FFFh
DARAM 2
00 4000h - 00 5FFFh
0001 4000h - 0001 5FFFh
DARAM 3
00 6000h - 00 7FFFh
0001 6000h - 0001 7FFFh
DARAM 4
00 8000h - 00 9FFFh
0001 8000h - 0001 9FFFh
DARAM 5
00 A000h - 00 BFFFh
0001 A000h - 0001 BFFFh
(1)
First 192 bytes are reserved for memory-mapped registers (MMRs).
17
SPRUFX5A – October 2010 – Revised November 2010
System Control
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