Texas Instruments TMS3320C5515 사용자 설명서

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1.1

Introduction

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1.1.1

Block Diagram

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1.1.2

CPU Core

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1.1.3

FFT Hardware Accelerator

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1.1.4

Power Management

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1.1.5

Peripherals

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1.2

System Memory

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1.2.1

Program/Data Memory Map

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1.2.2

I/O Memory Map

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1.3

Device Clocking

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1.3.1

Overview

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1.3.2

Clock Domains

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1.4

System Clock Generator

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1.4.1

Overview

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1.4.2

Functional Description

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1.4.3

Configuration

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1.4.4

Clock Generator Registers

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1.5

Power Management

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1.5.1

Overview

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1.5.2

Power Domains

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1.5.3

Clock Management

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1.5.4

Static Power Management

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1.5.5

Power Configurations

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1.6

Interrupts

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1.6.1

IFR and IER Registers

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1.6.2

Interrupt Timing

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1.6.3

Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h]

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1.6.4

GPIO Interrupt Enable and Aggregation Flag Registers

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1.6.5

DMA Interrupt Enable and Aggregation Flag Registers

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1.7

System Configuration and Control

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1.7.1

Overview

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1.7.2

Device Identification

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1.7.3

Device Configuration

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1.7.4

DMA Controller Configuration

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1.7.5

Peripheral Reset

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1.7.6

EMIF and USB Byte Access

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1.7.7

EMIF Clock Divider Register (ECDR) [1C26h]

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3

SPRUFX5A – October 2010 – Revised November 2010

Copyright © 2010, Texas Instruments Incorporated