Intel SR1630BC 사용자 설명서
Appendix B: POST Code Diagnostic LED Decoder
Intel® Server System SR1630BC TPS
Revision 1.5
Intel order number E44588-005
41
Table 25. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
O = On, X=Off
Upper Nibble
Lower Nibble
MSB
LSB
Checkpoint
8h 4h 2h 1h 8h 4h 2h 1h
LED
#7 #6 #5 #4 #3 #2 #1 #0
Description
Multi-use code – This POST Code is used in different contexts
.
0xF2h
O
O
O
O
X
X
O
X
Seen at the start of Memory Reference Code (MRC)
Start of the very early platform initialization code
Very late in POST, it is the signal that the operating system has
switched to virtual memory mode
switched to virtual memory mode
Memory Error Codes (Accompanied by a beep code)
Note that these are codes used in early POST by Memory Reference Code. Later in POST these same codes are used for
other Progress Codes. (These progress codes are not controlled by BIOS and are subject to change at the discretion of
the Memory Reference Code team.)
Note that these are codes used in early POST by Memory Reference Code. Later in POST these same codes are used for
other Progress Codes. (These progress codes are not controlled by BIOS and are subject to change at the discretion of
the Memory Reference Code team.)
0xE8h
O O O X O X X X
No Usable Memory Error: No memory in the system, or SPD bad so
no memory could be detected
no memory could be detected
0xEAh
O O O X O X O X
Channel Training Error: DQ/DQS training failed on a channel during
memory channel initialization. If no usable memory remains, system
is halted.
memory channel initialization. If no usable memory remains, system
is halted.
0xEBh O O O X O X O O Memory
Test
Error: memory failed Hardware BIST.
0xEDh
O O O X O O X O
Population Error: RDIMMs and UDIMMs cannot be mixed in the
system
system
0xEEh O O O X O O O X Mismatch
Error:
more than 2 Quad Ranked DIMMS in a channel.
Memory Reference Code Progress Codes (Not accompanied by a beep code)
0xB0h O X O O X X X X Chipset
Initialization
Phase
0xB1h O X O O X X X O Reset
Phase
0xB2h O X O O X X O X DIMM
Detection
Phase
0xB3h O X O O X X O O Clock
Initialization
Phase
0Xb4h O X O O X O X X SPD
Data
Collection
Phase
0Xb6h O X O O X O O X Rank Formation Phase
0xB8h O X O O O X X X Channel
0xB8h O X O O O X X X Channel
Training
Phase
0xB9h O X O O O X X O Memory
Test
Phase
0xBAh O X O O O X O X Memory
Map
Creation
Phase
0xBBh O X O O O X O O RAS
Initialization
Phase
0xBCh O X O O O O X X MRC
Complete
Host Processor
0x04h X X X O X O X X
Early processor initialization (flat32.asm) where system BSP is
selected
selected
0x10h X X X O X X X X Power-on
initialization of the host processor (bootstrap processor)
0x11h X X X O X X X O Host
processor
cache initialization (including AP)
0x12h X X X O X X O X Starting
application processor initialization
0x13h X X X O X X O O SMM
initialization
Chipset
0x21h X X O X X X X O Initializing
a
chipset
component
Memory
0x22h
X
X
O
X
X
X
O
X
Reading configuration data from memory (SPD on DIMM)
0x23h X X O X X X O O Detecting
presence
of
memory
0x24h X X O X
X O X X Programming
timing
parameters in the memory controller
0x25h X X O X X O X O Configuring
memory parameters in the memory controller
0x26h X X O X X O O X Optimizing
memory
controller
settings
0x27h
X
X
O
X
X
O
O
O
Initializing memory, such as ECC init
0x28h X X O X O X X X Testing
memory
PCI Bus
0x50h X O X O X X X X Enumerating PCI buses
0x51h X O X O X X X O Allocating
0x51h X O X O X X X O Allocating
resources
to
PCI
buses