AMD Typewriter x86 사용자 설명서

AMD

Revision History

xv

22007E/0—November 1999

AMD Athlon™ Processor x86 Code Optimization

Revision History

Date

Rev

Description

Nov.

1999

E

Added “A bout this D o cument” on page 1.

Further clarification of “Consider the Sign of Integer Operands” on page 14.

Added the optimization, “Use Array Style Instead of Pointer Style Code” on page 15.

Added the optimization, “Accelerating Floating-Point Divides and Square Roots” on page 29.

Clarified examples in “Copy Frequently De-refer enced Pointer Arguments to Local Variables” on page 31.

Further clarification of “Selec t DirectPath Over VectorPath Inst ructions” on page 34.

Further clarification of “Align Branch T a rgets in Progra m Hot Spots” on page 36.

Further clarification of RE P instruction as a filler in “Code Padding Using Neutral Code Fil lers” on page 39.

Further clarification of “Use the 3DNow!™ P REFETCH and PR EFETCHW Instructions” on page 46.

Modified examples 1 an d 2 of “Unsigned Division by Multiplication of Constant” on page 78.

Added the optimization, “E fficient Implementation of Population Count F unction” on page 91.

Further clarification of “U se FFREEP Macro to Pop One Register from the FPU Stack” on page 98.

Further cl arification of “Minimize Floating-Point-to-Int eger Conversions” on page 1 00.

Added the optimization, “Check Argument Range of Trigonometric Instructions Efficiently” on page 103.

Added the optimization, “T ake Advantage of the FSINCOS Instruction” on page 105.

Further clarification of “Use 3DNow!™ Instructions for Fast D ivision” on page 108.

Further clarification “Use FEMMS Instruction” on page 107.

Further clarification of “Use 3DNow!™ Instructions for Fast Square Root and Rec iprocal Square Root” on
page 110.

Clarified “3DNow!™ and MMX™ Intra-Operand Swapping” on page 112.

Corr ected PCMPGT information in “Use MMX™ PCMP Instead of 3DNow!™ P FCMP” on page 1 14.

Added the optimization, “Use MMX™ Instructions for Block Copies and Bloc k Fills” on page 115.

Modified the rule for “U se MMX™ PXOR to Clear All Bits in an MM X™ Register” on page 118.

Modified the rule for “U se MM X™ PCMPEQD to Set All Bits in an MMX™ Regis ter” on page 1 19.

Added the optimization, “Optimized Matrix Multiplication” on page 1 19.

Added the optimization, “Efficient 3D-Clipping Code Computation Using 3DNow!™ Instructions” on page
122.

Added the optimization, “C omplex Number Arithmetic” on page 126.

Added Appendix E, “Programming th e MTRR and PAT”.

Rearranged the appendices.

Added Index.