AMD Typewriter x86 사용자 설명서
Floating-Point Pipeline Stages
147
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
Cycle 7–STKREN
The stack rename (STKREN) pipeline stage in cycle 7 receives
up to three MacroOPs from IDEC and maps stack-relative
register tags to virtual register tags.
up to three MacroOPs from IDEC and maps stack-relative
register tags to virtual register tags.
Cycle 8–REGREN
The register renaming (REGREN) pipeline stage in cycle 8 is
responsible for register renaming. In this stage, virtual register
tags are mapped into physical register tags. Likewise, each
destination is assigned a new physical register. The MacroOPs
are then sent to the 36-entry FPU scheduler.
responsible for register renaming. In this stage, virtual register
tags are mapped into physical register tags. Likewise, each
destination is assigned a new physical register. The MacroOPs
are then sent to the 36-entry FPU scheduler.
Cycle 9–SCHEDW
The scheduler write (SCHEDW) pipeline stage in cycle 9 can
receive up to three MacroOPs per cycle.
receive up to three MacroOPs per cycle.
Cycle 10–SCHED
The schedule (SCHED) pipeline stage in cycle 10 schedules up
to three MacroOPs per cycle from the 36-entry FPU scheduler
to the FR EG pipe line stag e to re ad register o perands.
MacroOPs are sent when their operands and/or tags are
obtained.
to three MacroOPs per cycle from the 36-entry FPU scheduler
to the FR EG pipe line stag e to re ad register o perands.
MacroOPs are sent when their operands and/or tags are
obtained.
Cycle 11–FREG
The register file read (FREG) pipeline stage reads the
floating-point register file for any register source operands of
MacroOPs. The register file read is done before the MacroOPs
are sent to the floating-point execution pipelines.
floating-point register file for any register source operands of
MacroOPs. The register file read is done before the MacroOPs
are sent to the floating-point execution pipelines.
Cycle 12–15–
Floating-Point
Execution (FEXEC1–4)
The FPU has three logical pipes—FADD, FMUL, and FSTORE.
Each pipe may have several associated execution units. MMX
execution is in both the FADD and FMUL pipes, with the
exception of MMX instructions involving multiplies, which are
limited to the FMUL pipe. The FMUL pipe has special support
for long latency operations.
Each pipe may have several associated execution units. MMX
execution is in both the FADD and FMUL pipes, with the
exception of MMX instructions involving multiplies, which are
limited to the FMUL pipe. The FMUL pipe has special support
for long latency operations.
DirectPath/VectorPath operations are dispatched to the FPU
during cycle 6, but are not acted upon until they receive
validation from the ICU in cycle 7.
during cycle 6, but are not acted upon until they receive
validation from the ICU in cycle 7.