AMD Typewriter x86 사용자 설명서
Page Attribute Table (PAT)
177
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
not affected by this issue, only the variable range (and MTRR
DefType) registers are affected.
DefType) registers are affected.
Page Attribute Table (PAT)
The Page Attribute Table (PAT) is an extension of the page
table entry format, which allows the specification of memory
types to regions of physical memory based on the linear
address. The PAT provides the same functionality as MTRRs
with the flexibility of the page tables. It provides the operating
systems and applications to determine the desired memory
type for optimal performance. PAT support is detected in the
feature flags (bit 16) of the CPUID instruction.
table entry format, which allows the specification of memory
types to regions of physical memory based on the linear
address. The PAT provides the same functionality as MTRRs
with the flexibility of the page tables. It provides the operating
systems and applications to determine the desired memory
type for optimal performance. PAT support is detected in the
feature flags (bit 16) of the CPUID instruction.
MSR Access
The PAT is located in a 64-bit MSR at location 277h. It is
illustrated in Figure 15. Each of the eight PAn fields can contain
the memory type encodings as described in Table 12 on
page 174. An attempt to write an undefined memory type
encoding into the PAT will generate a GP fault.
illustrated in Figure 15. Each of the eight PAn fields can contain
the memory type encodings as described in Table 12 on
page 174. An attempt to write an undefined memory type
encoding into the PAT will generate a GP fault.
Figure 15. Page Attribute Table (MSR 277h)
2
0
31
PA0
Reserved
10
8
18
16
26
24
PA1
PA2
PA3
34
32
63
PA4
42
40
50
48
58
56
PA5
PA6
PA7