AMD Typewriter x86 사용자 설명서

22007E/0—November 1999

In general, avoid misaligned data references. All data whose
size is a power of 2 is considered aligned if it is naturally
aligned. For example:

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QWORD accesses are aligned if they access an address
divisible by 8.

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DWORD accesses are aligned if they access an address
divisible by 4.

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WORD accesses are aligned if they access an address
divisible by 2.

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TBYTE accesses are aligned if they access an address
divisible by 8.

A misaligned store or load operation suffers a minimum
one-cycle penalty in the AMD Athlon processor load/store
pipeline. In addition, using misaligned loads and stores
increases the likelihood of encountering a store-to-load
forwarding pitfall. For a more detailed discussion of store-to-
loa d forwarding issues,  see  “Store -to-L oad Forwarding
Restrictions” on page 51.

For code that can take advantage of prefetching, use the
3DNow!  PREFE TCH and PRE FET CHW instructio ns to
increase the effective bandwidth to the AMD Athlon processor.
Th e   P R E F E T C H   a n d   P R E F E T C H W   i n s t r u c t i o n s   t a ke
advantage of the AMD Athlon processor’s high bus bandwidth
to hide long latencies when fetching data from system memory.
The prefetch instructions are essentially integer instructions
and can be used anywhere, in any type of code (integer, x87,
3DNow!, MMX, etc.).

Large data sets typically require unit-stride access to ensure
that all data pulled in by PREFETCH or PREFETCHW is
actually used. If necessary, algorithms or data structures should
be reorganized to allow unit-stride access.

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