AMD Typewriter x86 사용자 설명서
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
Schedule Instructions According to their Latency
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Scheduling Optimizations
This chapter describes how to code instructions for efficient
scheduling. Guidelines are listed in order of importance.
scheduling. Guidelines are listed in order of importance.
Schedule Instructions According to their Latency
The AMD Athlon™ processor can execute up to three x86
instructions per cycle, with each x86 instruction possibly having
a different latency. The AMD Athlon processor has flexible
scheduling, but for absolute maximum performance, schedule
instructions, especially FPU and 3DNow!™ instructions,
according to their latency. Dependent instructions will then not
have to wait on instructions with longer latencies.
instructions per cycle, with each x86 instruction possibly having
a different latency. The AMD Athlon processor has flexible
scheduling, but for absolute maximum performance, schedule
instructions, especially FPU and 3DNow!™ instructions,
according to their latency. Dependent instructions will then not
have to wait on instructions with longer latencies.
Se e Appendix F, “Instruction Dispatch and Execution
Resources” on page 187 for a list of latency numbers.
Resources” on page 187 for a list of latency numbers.
Unrolling Loops
Complete Loop Unrolling
Make use of the large AMD Athlon processor 64-Kbyte
instruction cache and unroll loops to get more parallelism and
reduce loop overhead, even with branch prediction. Complete
instruction cache and unroll loops to get more parallelism and
reduce loop overhead, even with branch prediction. Complete