Xilinx XAPP169 사용자 설명서

XAPP169 (v1.0) November 24, 1999

11

1-800-255-7778

R

The USB interface in the design is based on a National Semiconductor USBN9602 controller. 
This device, packaged in a 28-pin SOIC package, supports full speed USB function controller 
operation and includes an integrated USB transceiver. It contains seven endpoint FIFOs, two of 
which are 64 bytes deep.

 shows a block diagram of this device. The complete data sheet for the USBN9602 

can be found at the following URL:

The system interface for the USBN9602 is a simple 8-bit microprocessor bus that can be 
configured to operate in a multiplexed or non-multiplexed mode. The multiplexed mode is more 
attractive from a software perspective since it supports random access to the devices’ internal 
registers. This mode also reduces the number of interface pins required. For both of these 
reasons this was chosen for this application. 

 shows read timing for the USBN9602 

when operating in multiplexed mode.

Physical Layer Interface (PHY)

Media Access Controller (MAC)

Transceiver

48 MHz

Oscillator

Clock

Generator

XIN

XOUT

CLKOUT

Microcontroller Interface

D+

D-

Upstream Port

INTR

V3.3

CS

RD

WR

 A0/ALE

 D[7:0]/AD[7:0]

EP

2

E

n

d

poi

nt

0

EP

1

EP

6

EP

5

RX

TX

VReg

AGND

RESET

Vcc

GND

MODE[1:0]

Status

Control

USB Event

Detect

Clock

Recovery

EP

4

EP3

 (Courtesy National Semiconductor)