Texas Instruments TMS320C6712D 사용자 설명서

           

SPRS293 − OCTOBER 2005

91

POST OFFICE BOX 1443 

•

 HOUSTON, TEXAS 77251−1443

1

th(CKXL-FXL)

Hold time, FSX low 
after CLKX low¶

L − 2

L + 3

ns

2

td(FXL-CKXH)

Delay time, FSX low to CLKX high#

T − 2

T + 3

ns

3

td(CKXL-DXV)

Delay time, CLKX low to DX valid

−3

4

6P + 2

10P + 17

ns

6

tdis(CKXL-DXHZ)

Disable time, DX high impedance following last data bit from
CLKX low

−2

4

6P + 3

10P + 17

ns

7

td(FXL-DXV)

Delay time, FSX low to DX valid

H − 2

H + 6.5

4P + 2

8P + 17

ns

† P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)

=

Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T =

CLKX period = (1 + CLKGDV) * S

H =

CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L =

CLKX low pulse width

= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).