Renesas R5S72641 사용자 설명서
Section 27 Video Display Controller 3
Page 1606 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7
WE
0
R/W
Enables transfer of the
control register values.
Writing 1 to this bit transfers the register values
(GROPEDPA register to GROPCRKY1 register) in
synchronization with Vsync. After register transfer
is competed, this bit is cleared to 0.
(GROPEDPA register to GROPCRKY1 register) in
synchronization with Vsync. After register transfer
is competed, this bit is cleared to 0.
0: Disabled
1: Enabled
6, 5
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
4 AST 0 R
Blending Status Flag
0: Addition or subtraction has been completed.
1: Addition or subtraction is in progress
3
0 R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
2, 1
AMOD[1:0] 00
R/W
These bits specify the
processing mode.
00: Initial
value (the value does not change)
01:
value addition
10:
value subtraction
11: Setting prohibited
0
AEN
0
R/W
Enables or disables
control.
0:
control is disabled.*
1:
control is enabled.
Note: * When 0 is specified, either the replaced
value after chroma-keying or the dot
function is valid. If neither
function is
used, the
control processing becomes
the same as when
= 255.