Texas Instruments SM320F2812-HT 사용자 설명서

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle

before an access to meet this requirement.

B. During alignment cycles, all signals transitions to their inactive state.

C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.

SGUS062A – JUNE 2009 – REVISED APRIL 2010

XTIMING register parameters used for this example:

≥

1

≥

0

≥

0

0

0

N/A

(1)

N/A

(1)

N/A

(1)

N/A

(1)

(1)

N/A = "Don't care" for this example

t

d(XCOH-XZCSL)

Delay time, XCLKOUT high to zone chip-select active low

1

ns

t

d(XCOHL-XZCSH)

Delay time, XCLKOUT high or low to zone chip-select inactive high

–2

3

ns

td(XCOH-XA)

Delay time, XCLKOUT high to address valid

2

ns

t

d(XCOHL-XWEL)

Delay time, XCLKOUT high/low to XWE low

2

ns

t

d(XCOHL-XWEH)

Delay time, XCLKOUT high/low to XWE high

2

ns

t

d(XCOH-XRNWL)

Delay time, XCLKOUT high to XR/W low

1

ns

t

d(XCOHL-XRNWH)

Delay time, XCLKOUT high/low to XR/W high

–2

1

ns

t

en(XD)XWEL

Enable time, data bus driven from XWE low

0

ns

t

d(XWEL-XD)

Delay time, data valid after XWE active low

4

ns

t

h(XA)XZCSH

Hold time, address valid after zone chip-select inactive high

(2)

ns

t

h(XD)XWE

Hold time, write data valid after XWE inactive high

TW–2

(3)

ns

t

dis(XD)XRNW

Data bus disabled after XR/W inactive high

4

ns

(1)

Not production tested.

(2)

During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

(3)

TW = Trail period, write access. See

.

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