Texas Instruments SM320F2812-HT 사용자 설명서

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment

cycle before an access to meet this requirement.

B. During alignment cycles, all signals transitions to their inactive state.

C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment

cycles.

D. For each sample, setup time from the beginning of the access (D) can be calculated as:

  D = (XRDLEAD + XRDACTIVE +n − 1) t

c(XTIM)

 − t

su(XRDYsynchL)XCOHL

E. Reference for the first sample is with respect to this point

  E = (XRDLEAD + XRDACTIVE)  t

c(XTIM)

where n is the sample number: n = 1, 2, 3, and so forth.

 = Don’t care. Signal can be high or low during this time.

SGUS062A – JUNE 2009 – REVISED APRIL 2010

t

su(XRDYAsynchH)XCOHL

Setup time, XREADY (Asynch) high before XCLKOUT high/low

11

ns

t

h(XRDYasynchH)XZCSH

Hold time, XREADY (Asynch) held high after zone chip select high

0

ns

XTIMING register parameters used for this example:

0 = XREADY

≥

1

3

≥

1

1

0

N/A

(1)

N/A

(1)

N/A

(1)

(Synch)

(1)

N/A = "Don't care" for this example

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