Texas Instruments SM320F2812-HT 사용자 설명서
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SGUS062A – JUNE 2009 – REVISED APRIL 2010
Table 6-53. McBSP Switching Characteristics
(1) (2) (3)
NO.
PARAMETER
MIN
MAX
UNIT
M1
t
c(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P
ns
M2
t
w(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D – 5
(4)
D + 5
(4)
ns
M3
t
w(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C – 5
(4)
C + 5
(4)
ns
CLKR int
0
4
M4
t
d(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
ns
CLKR ext
3
27
CLKX int
0
4
M5
t
d(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
ns
CLKX ext
3
27
CLKX int
8
Disable time, CLKX high to DX high impedance following last
M6
t
dis(CKXH-DXHZ)
ns
data bit
CLKX ext
14
CLKX int
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
This applies to all bits except the first bit transmitted.
CLKX ext
28
CLKX int
8
M7
t
d(CKXH-DXV)
Delay time, CLKX high to DX valid
DXENA = 0
ns
CLKX ext
14
CLKX int
P + 8
Only applies to first bit transmitted when in Data
DXENA = 1
Delay 1 or 2 (XDATDLY= 01b or 10b) modes
CLKX ext
P + 14
CLKX int
0
Enable time, CLKX high to DX driven
DXENA = 0
CLKX ext
6
M8
t
en(CKXH-DX)
ns
CLKX int
P
Only applies to first bit transmitted when in Data
DXENA = 1
Delay 1 or 2 (XDATDLY= 01b or 10b) modes
CLKX ext
P + 6
FSX int
8
Delay time, FSX high to DX valid
DXENA = 0
FSX ext
14
M9
t
d(FXH-DXV)
ns
FSX int
P + 8
Only applies to first bit transmitted when in Data
DXENA = 1
Delay 0 (XDATDLY= 00b) mode.
FSX ext
P + 14
FSX int
0
Enable time, FSX high to DX driven
DXENA = 0
FSX ext
6
M10
t
en(FXH-DX)
ns
FSX int
P
Only applies to first bit transmitted when in Data
DXENA = 1
Delay 0 (XDATDLY= 00b) mode
FSX ext
P + 6
(1)
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
signal are also inverted.
(2)
2P = 1/CLKG in ns
(3)
Not production tested.
(4)
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
D = CLKRX high pulse width = P
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Electrical Specifications
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