Intel 4 551 BX80547PG3400EK 사용자 설명서

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BINIT#

Input/

Output

BINIT# (Bus Initialization) may be observed and driven by all processor FSB 
agents and if used, must connect the appropriate pins/lands of all such agents. 
If the BINIT# driver is enabled during power-on configuration, BINIT# is 
asserted to signal any bus condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration, and BINIT# is 
sampled asserted, symmetric agents reset their bus LOCK# activity and bus 
request arbitration state machines. The bus agents do not reset their IOQ and 
transaction tracking state machines upon observation of BINIT# activation. 
Once the BINIT# assertion has been observed, the bus agents will re-arbitrate 
for the FSB and attempt completion of their bus queue and IOQ entries.

If BINIT# observation is disabled during power-on configuration, a central agent 
may handle an assertion of BINIT# as appropriate to the error handling 
architecture of the system.

BNR#

Input/

Output

BNR# (Block Next Request) is used to assert a bus stall by any bus agent 
unable to accept new bus transactions. During a bus stall, the current bus 
owner cannot issue any new transactions.

BOOTSELECT

Input

This input is required to determine whether the processor is installed in a 
platform that supports the Pentium 4 processor in the 775-land package. The 
processor will not operate if this signal is low. This input has a weak internal 
pull-up to V

CC

.

BPM[5:0]#

Input/

Output

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor 
signals. They are outputs from the processor which indicate the status of 
breakpoints and programmable counters used for monitoring processor 
performance. BPM[5:0]# should connect the appropriate pins/lands of all 
processor FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# 
is a processor output used by debug tools to determine processor debug 
readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. 
PREQ# is used by debug tools to request debug operation of the processor.

These signals do not have on-die termination. Refer to 

termination requirements.

BPRI#

Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor 
FSB. It must connect the appropriate pins/lands of all processor FSB agents. 
Observing BPRI# active (as asserted by the priority agent) causes all other 
agents to stop issuing new requests, unless such requests are part of an 
ongoing locked operation. The priority agent keeps BPRI# asserted until all of 
its requests are completed, then releases the bus by de-asserting BPRI#.

BR0#

Input/

Output

BR0# drives the BREQ0# signal in the system and is used by the processor to 
request the bus. During power-on configuration this signal is sampled to 
determine the agent ID = 0. 

This signal does not have on-die termination and must be terminated.

BSEL[2:0]

Output

The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the 
processor input clock frequency. 

 defines the possible combinations of 

the signals and the frequency associated with each combination. The required 
frequency is determined by the processor, chipset and clock synthesizer. All 
agents must operate at the same frequency. For more information about these 
signals, including termination recommendations refer to 

COMP[1:0]

Analog

COMP[1:0] must be terminated to V

SS 

on the system board using precision 

resistors.