Texas Instruments TMS320DM643x 사용자 설명서
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5.1
PLL Module
5.2
PLL1 Control
PLL Module
The DM643x DMP has two PLLs (PLL1 and PLL2) that provide clocks to different parts of the system.
PLL1 provides clocks (though various dividers) to most of the components of the DM643x DMP. PLL2 is
dedicated to the DDR2 port and components for the video processing subsystem (VPSS). The typical
reference clock is the 27 MHZ crystal input, as mentioned in
PLL1 provides clocks (though various dividers) to most of the components of the DM643x DMP. PLL2 is
dedicated to the DDR2 port and components for the video processing subsystem (VPSS). The typical
reference clock is the 27 MHZ crystal input, as mentioned in
.
The PLL controller provides the following:
•
Glitch-Free Transitions (on changing clock settings)
•
Domain Clocks Alignment
•
Clock Gating
•
PLL power down
The various clock outputs given by the controller are as follows:
•
Domain Clocks: SYSCLK[1:n]
•
Auxiliary Clock from reference clock source: AUXCLK
•
Bypass Domain clock: SYSCLKBP
•
Observe Clock: OBSCLK
Various dividers that can be used on the DM643x DMP are as follows:
•
PLL Controller Dividers (for SYSCLK[1:n]): PLLDIV1, ..., PLLDIVn
•
Bypass Divider (for SYSCLKBP): BPDIV
•
Oscillator Divider (for OBSCLK): OSCDIV1
Various other controls supported are as follows:
•
PLL Multiplier Control: PLLM
•
Software-programmable PLL Bypass: PLLEN
PLL1 supplies the primary DM643x DMP system clock. Software controls the PLL1 operation through the
system PLL controller 1 (PLLC1) registers. The registers used in PLLC1 are listed in
system PLL controller 1 (PLLC1) registers. The registers used in PLLC1 are listed in
shows the customization of PLL1 in the DM643x DMP. The domain clocks are distributed to the
core clock domains (discussed in
) and the rest of the device as follows:
•
SYSCLK1: CLKDIV1 Domain
•
SYSCLK2: CLKDIV3 Domain
•
SYSCLK3: CLKDIV6 Domain
•
AUXCLK: CLKIN Domain
•
OBSCLK: CLKOUT0 pin
•
SYSCLKBP: VPBE internal clock source
The PLL1 multiplier is controlled by the PLLM bit of the PLL multiplier control register (PLLM). The PLL1
output clock may be divided-down for slower device operation using the PLLC1 SYSCLK dividers
PLLDIV1, PLLDIV2, and PLLDIV3.
output clock may be divided-down for slower device operation using the PLLC1 SYSCLK dividers
PLLDIV1, PLLDIV2, and PLLDIV3.
You are responsible to adhere to the PLLC1 frequency ranges and multiplier/divider ratios specified in the
data manual. See also
data manual. See also
and
At power-up, PLL1 is powered-down and disabled, and must be powered-up by software through the PLL1
PLLPWRDN bit in the PLL control register (PLLCTL). By default, the system operates in bypass mode and
the system clock is provided directly from the input reference clock (MXI/CLKIN pin). Once the PLL is
powered-up and locked, software can switch the device to PLL mode operation by setting the PLLEN bit in
PLLCTL to 1. If the boot mode of the device is set to fast boot (FASTBOOT = 1), the bootloader code in
the Boot ROM will follow the previous process to power-up and lock the PLL, and switch the device to PLL
mode to speed up the boot process. Therefore, coming out of a fast boot, the device is operating in PLL
mode.
PLLPWRDN bit in the PLL control register (PLLCTL). By default, the system operates in bypass mode and
the system clock is provided directly from the input reference clock (MXI/CLKIN pin). Once the PLL is
powered-up and locked, software can switch the device to PLL mode operation by setting the PLLEN bit in
PLLCTL to 1. If the boot mode of the device is set to fast boot (FASTBOOT = 1), the bootloader code in
the Boot ROM will follow the previous process to power-up and lock the PLL, and switch the device to PLL
mode to speed up the boot process. Therefore, coming out of a fast boot, the device is operating in PLL
mode.
38
PLL Controller
SPRU978E – March 2008