Texas Instruments TMS320DM643x 사용자 설명서
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5.4.9 Bypass Divider Register (BPDIV)
PLL Controller Registers
The bypass divider register (BPDIV) is shown in
and described in
. Bypass divider
controls divider for SYSCLKBP, dividing down from the MXI/CLKIN clock.
Figure 5-11. Bypass Divider Register (BPDIV)
31
16
Reserved
R-0
15
14
5
4
0
BPDEN
Reserved
RATIO
R/W-1
R-0
R/W-0 or 1
(1)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
For PLLC1, RATIO defaults to 0 (MXI/CLKIN divide by 1); for PLLC2, RATIO defaults to 1 (MXI/CLKIN divide by 2).
Table 5-13. Bypass Divider Register (BPDIV) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15
BPDEN
Bypass divider enable.
0
Bypass divider is disabled.
1
Bypass divider is enabled.
14-5
Reserved
0
Reserved
4-0
RATIO
0-1Fh
Divider ratio. Divider value = RATIO + 1. For example, RATIO = 0 means divide by 1.
54
PLL Controller
SPRU978E – March 2008