Fujitsu MB91191 사용자 설명서
179
Figure 9.1-2 Block diagram of real timing generator (RTG)
IF
FCLR
IE
OUTE
TSEL
CLR
FUL
EMP
16bit
5bit
Comparator
EQ
Fifo
Control
FRC2-19
R Q
S
ADSTx
RTG2,3 Timing Select
RTG0x4-0
Output
(to MPX)
IRQx
(to I-unit)
RTOx4
Output Disable
Fi fo-o ut
Fifo-in
Write STB
RTGxC
MPX
Internal bus
Internal bus
Latch
R