Motorola MC68HC908MR32 사용자 설명서
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
102
System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
7.6.1.2 Software Interrupt (SWI) Instruction
The software interrupt (SWI) instruction is a non-maskable instruction
that causes an interrupt regardless of the state of the interrupt mask
(I bit) in the condition code register.
that causes an interrupt regardless of the state of the interrupt mask
(I bit) in the condition code register.
7.6.2 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
arbitrated.
7.7 Low-Power Mode
Executing the WAIT instruction puts the MCU in a low
power-consumption mode for standby situations. The SIM holds the
CPU in a non-clocked state. WAIT clears the interrupt mask (I) in the
condition code register, allowing interrupts to occur.
power-consumption mode for standby situations. The SIM holds the
CPU in a non-clocked state. WAIT clears the interrupt mask (I) in the
condition code register, allowing interrupts to occur.
7.7.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run.
continue to run.
shows the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.