Motorola MC68HC908MR32 사용자 설명서
Clock Generator Module (CGM)
CGM Registers
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
Advance Information
MOTOROLA
Clock Generator Module (CGM)
123
8.6 CGM Registers
These registers control and monitor operation of the CGM:
•
PLL control register (PCTL)
See
See
•
PLL bandwidth control register (PBWC)
See
See
•
PLL programming register (PPG)
See
See
is a summary of the CGM registers.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$005C
PLL Control Register
(PCTL)
Read:
PLLIE
PLLF
PLLON
BCS
1
1
1
1
Write:
R
R
R
R
R
Reset:
0
0
1
0
1
1
1
1
$005D
PLL Bandwidth Control Register
(PBWC)
Read:
AUTO
LOCK
ACQ
XLD
0
0
0
0
Write:
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
$005E
PLL Programming Register
(PPG)
Read:
MUL7
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
VRS4
Write:
Reset:
0
1
1
0
0
1
1
0
R
= Reserved
Notes:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 8-4. CGM I/O Register Summary