Motorola MC68HC908MR32 사용자 설명서
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
334
External Interrupt (IRQ)
MOTOROLA
External Interrupt (IRQ)
17.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) has these functions:
•
Clears the IRQ interrupt latch
•
Masks IRQ interrupt requests
•
Controls triggering sensitivity of the IRQ interrupt pin
ACK1 — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1
always reads as logic 0. Reset clears ACK1.
always reads as logic 0. Reset clears ACK1.
IMASK1 — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK1.
Reset clears IMASK1.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
0 = IRQ interrupt requests enabled
MODE1 — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE1.
Reset clears MODE1.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
0 = IRQ interrupt requests on falling edges only
IRQF — IRQ Flag
This read-only bit acts as a status flag, indicating an IRQ event
occurred.
occurred.
1 = External IRQ event occurred.
0 = External IRQ event did not occur.
0 = External IRQ event did not occur.
Address:
$003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
IRQF
0
IMASK1
MODE1
Write:
R
R
R
R
ACK1
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 17-4. IRQ Status and Control Register (ISCR)