Motorola MC68HC908MR32 사용자 설명서
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
338
Low-Voltage Inhibit (LVI)
MOTOROLA
Low-Voltage Inhibit (LVI)
18.4.4 LVI Trip Selection
The TRPSEL bit allows the user to chose between 5 percent and
10 percent tolerance when monitoring the supply voltage. The
10 percent option is enabled out of reset. Writing a logic 1 to TRPSEL
will enable 5 percent option.
10 percent tolerance when monitoring the supply voltage. The
10 percent option is enabled out of reset. Writing a logic 1 to TRPSEL
will enable 5 percent option.
NOTE:
The microcontroller is guaranteed to operate at a minimum supply
voltage. The trip point (VLVR1 or VLVR2) may be lower than this.
See
voltage. The trip point (VLVR1 or VLVR2) may be lower than this.
See
18.5 LVI Status and Control Register
The LVI status register (LVISCR) flags V
DD
voltages below the V
LVRX
level
.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
DD
voltage falls below the
V
LVRX
voltage for 32 to 40 CGMXCLK cycles. See
clears the LVIOUT bit.
Address:
$FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
TRPSEL
0
0
0
0
0
Write:
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 18-3. LVI Status and Control Register (LVISCR)