Motorola MC68HC908MR32 사용자 설명서
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
362
Break Module (BRK)
MOTOROLA
Break Module (BRK)
21.4.1 Flag Protection During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.
software to clear status bits during the break state.
21.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
21.4.3 TIM1 and TIM2 During Break Interrupts
A break interrupt stops the timer counters.
21.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
TST
is present on
the RST pin.
21.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
consumption standby modes.
21.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set. Clear the BW bit by writing logic 0 to it.
the user can subtract one from the return address on the stack if SBSW
is set. Clear the BW bit by writing logic 0 to it.