Motorola MC68HC908MR32 사용자 설명서
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
68
Configuration Register (CONFIG)
MOTOROLA
Configuration Register (CONFIG)
NOTE:
On a FLASH device, the options are one-time writeable by the user after
each reset. The registers are not in the FLASH memory but are special
registers containing one-time writeable latches after each reset. Upon a
reset, the configuration register defaults to predetermined settings as
shown in
each reset. The registers are not in the FLASH memory but are special
registers containing one-time writeable latches after each reset. Upon a
reset, the configuration register defaults to predetermined settings as
shown in
If the LVI module and the LVI reset signal are enabled, a reset occurs
when V
when V
DD
falls to a voltage, V
LVRx
, and remains at or below that level for
at least nine consecutive central processor unit (CPU) cycles. Once an
LVI reset occurs, the MCU remains in reset until V
LVI reset occurs, the MCU remains in reset until V
DD
rises to a voltage,
V
LVRX
.
5.4 Configuration Register
EDGE — Edge-Align Enable Bit
EDGE determines if the motor control PWM will operate in
edge-aligned mode or center-aligned mode. See
edge-aligned mode or center-aligned mode. See
.
1 = Edge-aligned mode enabled
0 = Center-aligned mode enabled
0 = Center-aligned mode enabled
BOTNEG — Bottom-Side PWM Polarity Bit
BOTNEG determines if the bottom-side PWMs will have positive or
negative polarity. See
negative polarity. See
.
1 = Negative polarity
0 = Positive polarity
0 = Positive polarity
Address:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EDGE
BOTNEG TOPNEG
INDEP
LVIRST
LVIPWR
STOPE
COPD
Write:
Reset:
0
0
0
0
1
1
0
0
Figure 5-1. Configuration Register (CONFIG)