Motorola MC68HC908MR32 사용자 설명서
System Integration Module (SIM)
Reset and System Initialization
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
Advance Information
MOTOROLA
System Integration Module (SIM)
93
7.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See
7.3.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 CGMXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The internal bus (IBUS) clocks start upon
completion of the timeout.
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 CGMXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The internal bus (IBUS) clocks start upon
completion of the timeout.
7.3.3 Clocks in Wait Mode
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
7.4 Reset and System Initialization
The MCU has these reset sources:
•
Power-on reset module (POR)
•
External reset pin (RST)
•
Computer operating properly (COP) module
•
Low-voltage inhibit (LVI) module
•
Illegal opcode
•
Illegal address