데이터 시트 (S26361-F3250-L160)차례Dual-Core Intel® Xeon® Processor 5100 Series1Contents3Figures4Table5Revision History7Features91 Introduction111.1 Terminology121.2 State of Data141.3 References142 Electrical Specifications172.1 Front Side Bus and GTLREF172.2 Power and Ground Lands172.3 Decoupling Guidelines182.3.1 VCC Decoupling182.3.2 VTT Decoupling182.3.3 Front Side Bus AGTL+ Decoupling182.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking182.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])192.4.2 PLL Power Supply202.5 Voltage Identification (VID)202.6 Reserved or Unused Signals232.7 Front Side Bus Signal Groups242.8 CMOS Asynchronous and Open Drain Asynchronous Signals252.9 Test Access Port (TAP) Connection252.10 Platform Environmental Control Interface (PECI) DC Specifications262.10.1 DC Characteristics262.10.2 Input Device Hysteresis272.11 Mixing Processors272.12 Absolute Maximum and Minimum Ratings272.13 Processor DC Specifications292.13.1 VCC Overshoot Specification352.13.2 Die Voltage Validation363 Mechanical Specifications373.1 Package Mechanical Drawings373.2 Processor Component Keepout Zones413.3 Package Loading Specifications413.4 Package Handling Guidelines423.5 Package Insertion Specifications423.6 Processor Mass Specifications423.7 Processor Materials433.8 Processor Land Coordinates434 Land Listing454.1 Dual-Core Intel® Xeon® Processor 5100 Series Pin Assignments454.1.1 Land Listing by Land Name454.1.2 Land Listing by Land Number555 Signal Definitions655.1 Signal Definitions656 Thermal Specifications736.1 Package Thermal Specifications736.1.1 Thermal Specifications736.1.2 Thermal Metrology816.2 Processor Thermal Features826.2.1 Thermal Monitor Features826.2.2 On-Demand Mode846.2.3 PROCHOT# Signal856.2.4 FORCEPR# Signal856.2.5 THERMTRIP# Signal866.3 Platform Environment Control Interface (PECI)866.3.1 Introduction866.3.2 PECI Specifications887 Features917.1 Power-On Configuration Options917.2 Clock Control and Low Power States917.2.1 Normal State927.2.2 HALT or Extended HALT State927.2.3 Stop-Grant State947.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State957.3 Enhanced Intel SpeedStep® Technology958 Boxed Processor Specifications978.1 Introduction978.2 Mechanical Specifications998.2.1 Boxed Processor Heat Sink Dimensions (CEK)998.2.2 Boxed Processor Heat Sink Weight1078.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)1078.3 Electrical Requirements1078.3.1 Fan Power Supply (Active CEK)1078.3.2 Boxed Processor Cooling Requirements1088.4 Boxed Processor Contents1099 Debug Tools Specifications1119.1 Debug Port System Requirements1119.2 Target System Implementation1119.2.1 System Implementation1119.3 Logic Analyzer Interface (LAI)1119.3.1 Mechanical Considerations1129.3.2 Electrical Considerations112크기: 1.48메가바이트페이지: 112Language: English매뉴얼 열기
데이터 시트 (S26361-F3320-L160)차례Dual-Core Intel® Xeon® Processor 5100 Series1Contents3Figures4Table5Revision History7Features91 Introduction111.1 Terminology121.2 State of Data141.3 References142 Electrical Specifications172.1 Front Side Bus and GTLREF172.2 Power and Ground Lands172.3 Decoupling Guidelines182.3.1 VCC Decoupling182.3.2 VTT Decoupling182.3.3 Front Side Bus AGTL+ Decoupling182.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking182.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])192.4.2 PLL Power Supply202.5 Voltage Identification (VID)202.6 Reserved or Unused Signals232.7 Front Side Bus Signal Groups242.8 CMOS Asynchronous and Open Drain Asynchronous Signals252.9 Test Access Port (TAP) Connection252.10 Platform Environmental Control Interface (PECI) DC Specifications262.10.1 DC Characteristics262.10.2 Input Device Hysteresis272.11 Mixing Processors272.12 Absolute Maximum and Minimum Ratings272.13 Processor DC Specifications292.13.1 VCC Overshoot Specification352.13.2 Die Voltage Validation363 Mechanical Specifications373.1 Package Mechanical Drawings373.2 Processor Component Keepout Zones413.3 Package Loading Specifications413.4 Package Handling Guidelines423.5 Package Insertion Specifications423.6 Processor Mass Specifications423.7 Processor Materials433.8 Processor Land Coordinates434 Land Listing454.1 Dual-Core Intel® Xeon® Processor 5100 Series Pin Assignments454.1.1 Land Listing by Land Name454.1.2 Land Listing by Land Number555 Signal Definitions655.1 Signal Definitions656 Thermal Specifications736.1 Package Thermal Specifications736.1.1 Thermal Specifications736.1.2 Thermal Metrology816.2 Processor Thermal Features826.2.1 Thermal Monitor Features826.2.2 On-Demand Mode846.2.3 PROCHOT# Signal856.2.4 FORCEPR# Signal856.2.5 THERMTRIP# Signal866.3 Platform Environment Control Interface (PECI)866.3.1 Introduction866.3.2 PECI Specifications887 Features917.1 Power-On Configuration Options917.2 Clock Control and Low Power States917.2.1 Normal State927.2.2 HALT or Extended HALT State927.2.3 Stop-Grant State947.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State957.3 Enhanced Intel SpeedStep® Technology958 Boxed Processor Specifications978.1 Introduction978.2 Mechanical Specifications998.2.1 Boxed Processor Heat Sink Dimensions (CEK)998.2.2 Boxed Processor Heat Sink Weight1078.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)1078.3 Electrical Requirements1078.3.1 Fan Power Supply (Active CEK)1078.3.2 Boxed Processor Cooling Requirements1088.4 Boxed Processor Contents1099 Debug Tools Specifications1119.1 Debug Port System Requirements1119.2 Target System Implementation1119.2.1 System Implementation1119.3 Logic Analyzer Interface (LAI)1119.3.1 Mechanical Considerations1129.3.2 Electrical Considerations112크기: 1.48메가바이트페이지: 112Language: English매뉴얼 열기
데이터 시트 (S26361-F3243-L160)차례Dual-Core Intel® Xeon® Processor 5100 Series1Contents3Figures4Table5Revision History7Features91 Introduction111.1 Terminology121.2 State of Data141.3 References142 Electrical Specifications172.1 Front Side Bus and GTLREF172.2 Power and Ground Lands172.3 Decoupling Guidelines182.3.1 VCC Decoupling182.3.2 VTT Decoupling182.3.3 Front Side Bus AGTL+ Decoupling182.4 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking182.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0])192.4.2 PLL Power Supply202.5 Voltage Identification (VID)202.6 Reserved or Unused Signals232.7 Front Side Bus Signal Groups242.8 CMOS Asynchronous and Open Drain Asynchronous Signals252.9 Test Access Port (TAP) Connection252.10 Platform Environmental Control Interface (PECI) DC Specifications262.10.1 DC Characteristics262.10.2 Input Device Hysteresis272.11 Mixing Processors272.12 Absolute Maximum and Minimum Ratings272.13 Processor DC Specifications292.13.1 VCC Overshoot Specification352.13.2 Die Voltage Validation363 Mechanical Specifications373.1 Package Mechanical Drawings373.2 Processor Component Keepout Zones413.3 Package Loading Specifications413.4 Package Handling Guidelines423.5 Package Insertion Specifications423.6 Processor Mass Specifications423.7 Processor Materials433.8 Processor Land Coordinates434 Land Listing454.1 Dual-Core Intel® Xeon® Processor 5100 Series Pin Assignments454.1.1 Land Listing by Land Name454.1.2 Land Listing by Land Number555 Signal Definitions655.1 Signal Definitions656 Thermal Specifications736.1 Package Thermal Specifications736.1.1 Thermal Specifications736.1.2 Thermal Metrology816.2 Processor Thermal Features826.2.1 Thermal Monitor Features826.2.2 On-Demand Mode846.2.3 PROCHOT# Signal856.2.4 FORCEPR# Signal856.2.5 THERMTRIP# Signal866.3 Platform Environment Control Interface (PECI)866.3.1 Introduction866.3.2 PECI Specifications887 Features917.1 Power-On Configuration Options917.2 Clock Control and Low Power States917.2.1 Normal State927.2.2 HALT or Extended HALT State927.2.3 Stop-Grant State947.2.4 Extended HALT Snoop or HALT Snoop State, Stop Grant Snoop State957.3 Enhanced Intel SpeedStep® Technology958 Boxed Processor Specifications978.1 Introduction978.2 Mechanical Specifications998.2.1 Boxed Processor Heat Sink Dimensions (CEK)998.2.2 Boxed Processor Heat Sink Weight1078.2.3 Boxed Processor Retention Mechanism and Heat Sink Support (CEK)1078.3 Electrical Requirements1078.3.1 Fan Power Supply (Active CEK)1078.3.2 Boxed Processor Cooling Requirements1088.4 Boxed Processor Contents1099 Debug Tools Specifications1119.1 Debug Port System Requirements1119.2 Target System Implementation1119.2.1 System Implementation1119.3 Logic Analyzer Interface (LAI)1119.3.1 Mechanical Considerations1129.3.2 Electrical Considerations112크기: 1.48메가바이트페이지: 112Language: English매뉴얼 열기
