사용자 설명서차례Title Page1Copyright and Disclaimer2List of Figures13List of Tables15About This Manual19Who Should Read This Manual19Related Publications19Conventions Used in This Manual20Using This Manual with the Programming Environments Manual221. PowerPC 750GX Overview231.1 750GX Microprocessor Overview231.2 750GX Microprocessor Features251.2.1 Instruction Flow291.2.1.1 Instruction Queue and Dispatch Unit291.2.1.2 Branch Processing Unit (BPU)291.2.1.3 Completion Unit301.2.2 Independent Execution Units311.2.2.1 Integer Units (IUs)311.2.2.2 Floating-Point Unit (FPU)311.2.2.3 Load/Store Unit (LSU)321.2.2.4 System Register Unit (SRU)321.2.3 Memory Management Units (MMUs)321.2.4 On-Chip Level 1 Instruction and Data Caches331.2.5 On-Chip Level 2 Cache Implementation351.2.6 System Interface/Bus Interface Unit (BIU)351.2.7 Signals371.2.8 Signal Configuration381.2.9 Clocking401.3 750GX Microprocessor Implementation401.4 PowerPC Registers and Programming Model421.5 Instruction Set451.5.1 PowerPC Instruction Set451.5.2 750GX Microprocessor Instruction Set471.6 On-Chip Cache Implementation471.6.1 PowerPC Cache Model471.6.2 750GX Microprocessor Cache Implementation471.7 Exception Model481.7.1 PowerPC Exception Model481.7.2 750GX Microprocessor Exception Implementation491.8 Memory Management511.8.1 PowerPC Memory-Management Model511.8.2 750GX Microprocessor Memory-Management Implementation521.9 Instruction Timing521.10 Power Management541.11 Thermal Management551.12 Performance Monitor562. Programming Model572.1 PowerPC 750GX Processor Register Set572.1.1 Register Set572.1.2 PowerPC 750GX-Specific Registers642.1.2.1 Instruction Address Breakpoint Register (IABR)642.1.2.2 Hardware-Implementation-Dependent Register 0 (HID0)652.1.2.3 Hardware-Implementation-Dependent Register 1 (HID1)702.1.2.4 Hardware-Implementation-Dependent Register 2 (HID2)712.1.2.5 Performance-Monitor Registers722.1.3 Instruction Cache Throttling Control Register (ICTC)772.1.4 Thermal-Management Registers (THRMn)782.1.4.1 Thermal-Management Registers 1-2 (THRM1-THRM2)782.1.4.2 Thermal-Management Register 3 (THRM3)792.1.4.3 Thermal-Management Register 4 (THRM4)802.1.5 L2 Cache Control Register (L2CR)812.2 Operand Conventions822.2.1 Data Organization in Memory and Data Transfers822.2.2 Alignment and Misaligned Accesses822.2.3 Floating-Point Operand and Execution Models-UISA832.2.3.1 Denormalized Number Support832.2.3.2 Non-IEEE Mode (Nondenormalized Mode)832.2.3.3 Time-Critical Floating-Point Operation842.2.3.4 Floating-Point Storage Access Alignment842.2.3.5 Optional Floating-Point Graphics Instructions842.3 Instruction Set Summary862.3.1 Classes of Instructions872.3.1.1 Definition of Boundedly Undefined872.3.1.2 Defined Instruction Class872.3.1.3 Illegal Instruction Class882.3.1.4 Reserved Instruction Class892.3.2 Addressing Modes892.3.2.1 Memory Addressing892.3.2.2 Memory Operands892.3.2.3 Effective Address Calculation902.3.2.4 Synchronization902.3.3 Instruction Set Overview912.3.4 PowerPC UISA Instructions922.3.4.1 Integer Instructions922.3.4.2 Floating-Point Instructions952.3.4.3 Load-and-Store Instructions982.3.4.4 Branch and Flow-Control Instructions1062.3.4.5 System Linkage Instruction-UISA1082.3.4.6 Processor Control Instructions-UISA1082.3.4.7 Memory Synchronization Instructions-UISA1132.3.5 PowerPC VEA Instructions1132.3.5.1 Processor Control Instructions-VEA1132.3.5.2 Memory Synchronization Instructions-VEA1142.3.5.3 Memory Control Instructions-VEA1152.3.5.4 Optional External Control Instructions1172.3.6 PowerPC OEA Instructions1182.3.6.1 System Linkage Instructions-OEA1182.3.6.2 Processor Control Instructions-OEA1182.3.6.3 Memory Control Instructions-OEA1192.3.7 Recommended Simplified Mnemonics1203. Instruction-Cache and Data-Cache Operation1213.1 Data-Cache Organization1233.2 Instruction-Cache Organization1243.3 Memory and Cache Coherency1253.3.1 Memory/Cache Access Attributes (WIMG Bits)1253.3.2 MEI Protocol1263.3.2.1 MEI Hardware Considerations1283.3.3 Coherency Precautions in Single-Processor Systems1293.3.4 Coherency Precautions in Multiprocessor Systems1293.3.5 PowerPC 750GX-Initiated Load/Store Operations1303.3.5.1 Performed Loads and Stores1303.3.5.2 Sequential Consistency of Memory Accesses1303.3.5.3 Atomic Memory References1303.4 Cache Control1313.4.1 Cache-Control Parameters in HID01313.4.1.1 Data-Cache Flash Invalidation1323.4.1.2 Enabling and Disabling the Data Cache1323.4.1.3 Locking the Data Cache1323.4.1.4 Instruction-Cache Flash Invalidation1333.4.1.5 Enabling and Disabling the Instruction Cache1333.4.1.6 Locking the Instruction Cache1333.4.2 Cache-Control Instructions1333.4.2.1 Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst)1343.4.2.2 Data Cache Block Zero (dcbz)1343.4.2.3 Data Cache Block Store (dcbst)1353.4.2.4 Data Cache Block Flush (dcbf)1353.4.2.5 Data Cache Block Invalidate (dcbi)1353.4.2.6 Instruction Cache Block Invalidate (icbi)1363.5 Cache Operations1363.5.1 Cache-Block-Replacement/Castout Operations1363.5.2 Cache Flush Operations1383.5.3 Data-Cache Block-Fill Operations1393.5.4 Instruction-Cache Block-Fill Operations1393.5.5 Data-Cache Block-Push Operations1393.6 L1 Caches and 60x Bus Transactions1393.6.1 Read Operations and the MEI Protocol1403.6.2 Bus Operations Caused by Cache-Control Instructions1413.6.3 Snooping1423.6.4 Snoop Response to 60x Bus Transactions1433.6.5 Transfer Attributes1453.7 MEI State Transactions1474. Exceptions1514.1 PowerPC 750GX Microprocessor Exceptions1524.2 Exception Recognition and Priorities1534.3 Exception Processing1564.3.1 Machine Status Save/Restore Register 0 (SRR0)1564.3.2 Machine Status Save/Restore Register 1 (SRR1)1574.3.3 Machine State Register (MSR)1584.3.4 Enabling and Disabling Exceptions1604.3.5 Steps for Exception Processing1604.3.6 Setting MSR[RI]1614.3.7 Returning from an Exception Handler1614.4 Process Switching1624.5 Exception Definitions1624.5.1 System Reset Exception (0x00100)1634.5.1.1 Soft Reset1644.5.1.2 Hard Reset1644.5.2 Machine-Check Exception (0x00200)1674.5.2.1 Machine-Check Exception Enabled (MSR[ME] = 1)1684.5.2.2 Checkstop State (MSR[ME] = 0)1694.5.3 DSI Exception (0x00300)1694.5.4 ISI Exception (0x00400)1694.5.5 External Interrupt Exception (0x00500)1694.5.6 Alignment Exception (0x00600)1704.5.7 Program Exception (0x00700)1704.5.8 Floating-Point Unavailable Exception (0x00800)1714.5.9 Decrementer Exception (0x00900)1714.5.10 System Call Exception (0x00C00)1714.5.11 Trace Exception (0x00D00)1714.5.12 Floating-Point Assist Exception (0x00E00)1714.5.13 Performance-Monitor Interrupt (0x00F00)1724.5.14 Instruction Address Breakpoint Exception (0x01300)1734.5.15 System Management Interrupt (0x01400)1734.5.16 Thermal-Management Interrupt Exception (0x01700)1744.5.17 Data Address Breakpoint Exception1754.5.17.1 Data Address Breakpoint Register (DABR)1754.5.18 Soft Stops1754.5.19 Exception Latencies1764.5.20 Summary of Front-End Exception Handling1764.5.21 Timer Facilities1774.5.22 External Access Instructions1775. Memory Management1795.1 MMU Overview1795.1.1 Memory Addressing1815.1.2 MMU Organization1815.1.3 Address-Translation Mechanisms1865.1.4 Memory-Protection Facilities1875.1.5 Page History Information1885.1.6 General Flow of MMU Address Translation1895.1.6.1 Real-Addressing Mode and Block-Address-Translation Selection1895.1.6.2 Page-Address-Translation Selection1905.1.7 MMU Exceptions Summary1925.1.8 MMU Instructions and Register Summary1945.2 Real-Addressing Mode1955.3 Block-Address Translation1965.4 Memory Segment Model1965.4.1 Page History Recording1965.4.1.1 Referenced Bit1975.4.1.2 Changed Bit1985.4.1.3 Scenarios for Referenced and Changed Bit Recording1985.4.2 Page Memory Protection1995.4.3 TLB Description1995.4.3.1 TLB Organization1995.4.3.2 TLB Invalidation2015.4.4 Page-Address-Translation Summary2025.4.5 Page Table-Search Operation2045.4.6 Page Table Updates2075.4.7 Segment Register Updates2076. Instruction Timing2096.1 Terminology and Conventions2096.2 Instruction Timing Overview2116.3 Timing Considerations2156.3.1 General Instruction Flow2156.3.2 Instruction Fetch Timing2166.3.2.1 Cache Arbitration2176.3.2.2 Cache Hit2176.3.2.3 Cache Miss2226.3.2.4 L2 Cache Access Timing Considerations2246.3.2.5 Instruction Dispatch and Completion Considerations2246.3.2.6 Rename Register Operation2246.3.2.7 Instruction Serialization2256.4 Execution-Unit Timings2256.4.1 Branch Processing Unit Execution Timing2256.4.1.1 Branch Folding2266.4.1.2 Branch Instructions and Completion2276.4.1.3 Branch Prediction and Resolution2286.4.2 Integer Unit Execution Timing2326.4.3 Floating-Point Unit Execution Timing2326.4.4 Effect of Floating-Point Exceptions on Performance2326.4.5 Load/Store Unit Execution Timing2336.4.6 Effect of Operand Placement on Performance2336.4.7 Integer Store Gathering2346.4.8 System Register Unit Execution Timing2346.5 Memory Performance Considerations2356.5.1 Caching and Memory Coherency2356.5.2 Effect of TLB Miss2366.6 Instruction Scheduling Guidelines2366.6.1 Branch, Dispatch, and Completion-Unit Resource Requirements2376.6.1.1 Branch-Resolution Resource Requirements2376.6.1.2 Dispatch-Unit Resource Requirements2376.6.1.3 Completion-Unit Resource Requirements2376.7 Instruction Latency Summary2387. Signal Descriptions2497.1 Signal Configuration2507.2 Signal Descriptions2517.2.1 Address-Bus Arbitration Signals2517.2.1.1 Bus Request (BR)-Output2517.2.1.2 Bus Grant (BG)-Input2527.2.1.3 Address Bus Busy (ABB)2527.2.2 Address Transfer Start Signals2537.2.2.1 Transfer Start (TS)2537.2.3 Address Transfer Signals2547.2.3.1 Address Bus (A[0-31])2547.2.3.2 Address-Bus Parity (AP[0-3])2557.2.4 Address Transfer Attribute Signals2557.2.4.1 Transfer Type (TT[0-4])2567.2.4.2 Transfer Size (TSIZ[0-2])-Output2587.2.4.3 Transfer Burst (TBST)2597.2.4.4 Cache Inhibit (CI)-Output2607.2.4.5 Write-Through (WT)-Output2607.2.4.6 Global (GBL)2617.2.5 Address Transfer Termination Signals2627.2.5.1 Address Acknowledge (AACK)-Input2627.2.5.2 Address Retry (ARTRY)2637.2.6 Data-Bus Arbitration Signals2647.2.6.1 Data-Bus Grant (DBG)-Input2647.2.6.2 Data-Bus Write-Only (DBWO)2657.2.6.3 Data Bus Busy (DBB)2657.2.7 Data-Transfer Signals2667.2.7.1 Data Bus (DH[0-31], DL[0-31])2667.2.7.2 Data-Bus Parity (DP[0-7])2677.2.7.3 Data Bus Disable (DBDIS)-Input2687.2.8 Data-Transfer Termination Signals2687.2.8.1 Transfer Acknowledge (TA)-Input2687.2.8.2 Data Retry (DRTRY)-Input2697.2.8.3 Transfer Error Acknowledge (TEA)-Input2697.2.9 System Status Signals2707.2.9.1 Interrupt (INT)- Input2707.2.9.2 System Management Interrupt (SMI)-Input2707.2.9.3 Machine-Check Interrupt (MCP)-Input2717.2.9.4 Checkstop Input (CKSTP_IN)-Input2717.2.9.5 Checkstop Output (CKSTP_OUT)-Output2717.2.10 Reset Signals2727.2.10.1 Hard Reset (HRESET)-Input2727.2.10.2 Soft Reset (SRESET)-Input2727.2.11 Processor Status Signals2737.2.11.1 Quiescent Request (QREQ)-Output2737.2.11.2 Quiescent Acknowledge (QACK)-Input2737.2.11.3 Reservation (RSRV)-Output2737.2.11.4 Time Base Enable (TBEN)-Input2747.2.11.5 TLB Invalidate Synchronize (TLBISYNC)-Input2747.2.12 Processor Mode Selection Signals2747.2.13 I/O Voltage Select Signals2757.2.14 Test Interface Signals2757.2.14.1 IEEE 1149.1a-1993 Interface Description2757.2.14.2 LSSD_MODE2757.2.14.3 L1_TSTCLK2767.2.14.4 L2_TSTCLK2767.2.14.5 BVSEL2767.2.15 Clock Signals2767.2.15.1 System Clock (SYSCLK)-Input2777.2.15.2 Clock Out (CLK_OUT)-Output2777.2.15.3 PLL Configuration (PLL_CFG[0:4])-Input2777.2.15.4 PLL Range (PLL_RNG[0:1])-Input2787.2.16 Power and Ground Signals2788. Bus Interface Operation2798.1 Bus Interface Overview2808.1.1 Operation of the Instruction and Data L1 Caches2818.1.2 Operation of the Bus Interface2828.1.3 Bus Signal Clocking2828.1.4 Optional 32-Bit Data Bus Mode2828.1.5 Direct-Store Accesses2838.2 Memory-Access Protocol2848.2.1 Arbitration Signals2858.2.2 Miss-under-Miss2868.2.2.1 Miss-under-Miss and System Performance2878.2.2.2 Speculative Loads and Conditional Branches2908.3 Address-Bus Tenure2908.3.1 Address-Bus Arbitration2908.3.2 Address Transfer2928.3.2.1 Address-Bus Parity2948.3.2.2 Address Transfer Attribute Signals2948.3.2.3 Burst Ordering During Data Transfers2958.3.2.4 Effect of Alignment in Data Transfers2968.3.2.5 Alignment of External Control Instructions3008.3.3 Address Transfer Termination3008.4 Data-Bus Tenure3018.4.1 Data-Bus Arbitration3018.4.1.1 Using the DBB Signal3028.4.2 Data-Bus Write-Only3038.4.3 Data Transfer3038.4.4 Data-Transfer Termination3038.4.4.1 Normal Single-Beat Termination3048.4.4.2 Data-Transfer Termination Due to a Bus Error3078.4.5 Memory Coherency-MEI Protocol3088.5 Timing Examples3098.6 Optional Bus Configuration3168.6.1 32-Bit Data Bus Mode3168.6.2 No-DRTRY Mode3188.7 Processor State Signals3198.7.1 Support for the lwarx and stwcx. Instruction Pair3198.7.2 TLBISYNC Input3198.8 IEEE 1149.1a-1993 Compliant Interface3198.8.1 JTAG/COP Interface3198.9 Using Data-Bus Write-Only3209. L2 Cache3239.1 L2 Cache Overview3239.2 L2 Cache Operation3239.3 L2 Cache Control Register (L2CR)3299.4 L2 Cache Initialization3299.5 L2 Cache Global Invalidation3299.6 L2 Cache Used as On-Chip Memory3309.6.1 Locking the L2 Cache3309.6.1.1 Loading the Locked L2 Cache3319.6.1.2 Locked Cache Operation3319.7 Data-Only and Instruction-Only Modes3329.8 L2 Cache Test Features and Methods3329.8.1 L2CR Support for L2 Cache Testing3329.8.2 L2 Cache Testing3339.9 L2 Cache Timing33310. Power and Thermal Management33510.1 Dynamic Power Management33510.2 Programmable Power Modes33510.2.1 Power Management Modes33710.2.1.1 Full On Mode33710.2.1.2 Doze Mode33710.2.1.3 Nap Mode33710.2.1.4 Sleep Mode33910.2.1.5 Dynamic Power Reduction33910.2.2 Power Management Software Considerations34010.3 750GX Dual PLL Feature34010.3.1 Overview34010.3.2 Configuration Restriction on Frequency Transitions34110.3.3 Dual PLL Implementation34210.4 Thermal Assist Unit34310.4.1 Thermal Assist Unit Overview34310.4.2 Thermal Assist Unit Operation34410.4.2.1 TAU Single-Threshold Mode34510.4.2.2 TAU Dual-Threshold Mode34610.4.2.3 750GX Junction Temperature Determination34610.4.2.4 Power Saving Modes and TAU Operation34710.5 Instruction-Cache Throttling34711. Performance Monitor and System Related Features34911.1 Performance-Monitor Interrupt34911.2 Special-Purpose Registers Used by Performance Monitor35011.2.1 Performance-Monitor Registers35111.2.1.1 Monitor Mode Control Register 0 (MMCR0)35111.2.1.2 User Monitor Mode Control Register 0 (UMMCR0)35111.2.1.3 Monitor Mode Control Register 1 (MMCR1)35111.2.1.4 User Monitor Mode Control Register 1 (UMMCR1)35111.2.1.5 Performance-Monitor Counter Registers (PMCn)35111.2.1.6 User Performance-Monitor Counter Registers (UPMC1-UPMC4)35411.2.1.7 Sampled Instruction Address Register (SIA)35511.2.1.8 User Sampled Instruction Address Register (USIA)35511.3 Event Counting35511.4 Event Selection35611.5 Notes35611.6 Debug Support35711.6.1 Overview35711.6.2 Data-Address Breakpoint35711.7 JTAG/COP Functions35711.7.1 Introduction35711.7.2 Processor Resources Available through JTAG/COP Serial Interface35711.8 Resets35911.8.1 Hard Reset35911.8.2 Soft Reset35911.8.3 Reset Sequence36011.9 Checkstops36111.9.1 Checkstop Sources36111.9.2 Checkstop Control Bits36111.9.3 Open-Collector-Driver States during Checkstop36211.9.4 Vacancy Slot Application36211.10 750GX Parity36311.10.1 Parity Control and Status36411.10.2 Enabling Parity Error Detection36411.10.3 Parity Errors364Acronyms and Abbreviations365Index369Revision Log377크기: 3.58메가바이트페이지: 377Language: English매뉴얼 열기