Intel 2 Duo E7300 사용자 매뉴얼

차례

• 1 Introduction

  9
  • 1.1 Terminology

    10
    • 1.1.1 Processor Terminology Definitions

      10
  • 1.2 References

    12
• 2 Electrical Specifications

  13
  • 2.1 Power and Ground Lands

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  • 2.2 Decoupling Guidelines

    13
    • 2.2.1 VCC Decoupling

      13
    • 2.2.2 VTT Decoupling

      13
    • 2.2.3 FSB Decoupling

      14
  • 2.3 Voltage Identification

    14
  • 2.4 Reserved, Unused, and TESTHI Signals

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  • 2.5 Power Segment Identifier (PSID)

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  • 2.6 Voltage and Current Specification

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    • 2.6.1 Absolute Maximum and Minimum Ratings

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    • 2.6.2 DC Voltage and Current Specification

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    • 2.6.3 VCC Overshoot

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    • 2.6.4 Die Voltage Validation

      24
  • 2.7 Signaling Specifications

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    • 2.7.1 FSB Signal Groups

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    • 2.7.2 CMOS and Open Drain Signals

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    • 2.7.3 Processor DC Specifications

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      • 2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications

        29
      • 2.7.3.2 GTL+ Front Side Bus Specifications

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  • 2.8 Clock Specifications

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    • 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

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    • 2.8.2 FSB Frequency Select Signals (BSEL[2:0])

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    • 2.8.3 Phase Lock Loop (PLL) and Filter

      32
    • 2.8.4 BCLK[1:0] Specifications

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• 3 Package Mechanical Specifications

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  • 3.1 Package Mechanical Drawing

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  • 3.2 Processor Component Keep-Out Zones

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  • 3.3 Package Loading Specifications

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  • 3.4 Package Handling Guidelines

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  • 3.5 Package Insertion Specifications

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  • 3.6 Processor Mass Specification

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  • 3.7 Processor Materials

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  • 3.8 Processor Markings

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  • 3.9 Processor Land Coordinates

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• 4 Land Listing and Signal Descriptions

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  • 4.1 Processor Land Assignments

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  • 4.2 Alphabetical Signals Reference

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• 5 Thermal Specifications and Design Considerations

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  • 5.1 Processor Thermal Specifications

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    • 5.1.1 Thermal Specifications

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    • 5.1.2 Thermal Metrology

      81
  • 5.2 Processor Thermal Features

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    • 5.2.1 Thermal Monitor

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    • 5.2.2 Thermal Monitor 2

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    • 5.2.3 On-Demand Mode

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    • 5.2.4 PROCHOT# Signal

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    • 5.2.5 THERMTRIP# Signal

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  • 5.3 Platform Environment Control Interface (PECI)

    85
    • 5.3.1 Introduction

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      • 5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems

        85
    • 5.3.2 PECI Specifications

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      • 5.3.2.1 PECI Device Address

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      • 5.3.2.2 PECI Command Support

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      • 5.3.2.3 PECI Fault Handling Requirements

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      • 5.3.2.4 PECI GetTemp0() Error Code Support

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• 6 Features

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  • 6.1 Power-On Configuration Options

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  • 6.2 Clock Control and Low Power States

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    • 6.2.1 Normal State

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    • 6.2.2 HALT and Extended HALT Powerdown States

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      • 6.2.2.1 HALT Powerdown State

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      • 6.2.2.2 Extended HALT Powerdown State

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    • 6.2.3 Stop Grant and Extended Stop Grant States

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      • 6.2.3.1 Stop-Grant State

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      • 6.2.3.2 Extended Stop Grant State

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    • 6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State

      90
      • 6.2.4.1 HALT Snoop State, Stop Grant Snoop State

        90
      • 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State

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    • 6.2.5 Sleep State

      90
    • 6.2.6 Deep Sleep State

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    • 6.2.7 Deeper Sleep State

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    • 6.2.8 Enhanced Intel SpeedStep® Technology

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  • 6.3 Processor Power Status Indicator (PSI) Signal

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• 7 Boxed Processor Specifications

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  • 7.1 Introduction

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  • 7.2 Mechanical Specifications

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    • 7.2.1 Boxed Processor Cooling Solution Dimensions

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    • 7.2.2 Boxed Processor Fan Heatsink Weight

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    • 7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

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  • 7.3 Electrical Requirements

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    • 7.3.1 Fan Heatsink Power Supply

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  • 7.4 Thermal Specifications

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    • 7.4.1 Boxed Processor Cooling Requirements

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    • 7.4.2 Variable Speed Fan

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• 8 Debug Tools Specifications

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  • 8.1 Logic Analyzer Interface (LAI)

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    • 8.1.1 Mechanical Considerations

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    • 8.1.2 Electrical Considerations

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