Intel 9560 사용자 매뉴얼

차례

• 0Intel® Itanium® Processor 9300 Series and 9500 Series

  1
• 1 Introduction

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  • 1.1 Overview

    9
  • 1.2 Architectural Overview

    15
    • 1.2.1 Intel® Itanium® Processor 9300 Series Overview

      15
    • 1.2.2 Intel® Itanium® Processor 9500 Series Overview

      16
  • 1.3 Processor Feature Comparison

    19
  • 1.4 Processor Abstraction Layer

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  • 1.5 Mixing Processors of Different Frequencies and Cache Sizes

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  • 1.6 Terminology

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  • 1.7 State of Data

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  • 1.8 Reference Documents

    21
• 2 Electrical Specifications

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  • 2.1 Intel® QuickPath Interconnect and Intel® Scalable Memory Interconnect Differential Signaling

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  • 2.2 Signal Groups

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  • 2.3 Reference Clocking Specifications

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  • 2.4 Intel® QuickPath Interconnect and Intel® SMI Signaling Specifications

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    • 2.4.1 Intel® Itanium® Processor 9300 Series Intel® QuickPath Interconnect and Intel® SMI Specifications for 4.8 GT/s

      28
    • 2.4.2 Intel® Itanium® Processor 9500 Series Requirements for Intel® QuickPath Interconnect for 4.8 and 6.4 GT/s

      32
    • 2.4.3 Intel® Itanium® Processor 9500 Series Processor Requirements for Intel® SMI Specifications for 6.4 GT/s

      37
  • 2.5 Processor Absolute Maximum Ratings

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    • 2.5.1 Intel® Itanium® Processor 9300 Series Absolute Maximum Ratings

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    • 2.5.2 Intel® Itanium® Processor 9500 Series Absolute Maximum Ratings

      39
  • 2.6 Processor DC Specifications

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    • 2.6.1 Flexible Motherboard Guidelines for the Intel® Itanium® Processor 9300 Series

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    • 2.6.2 Flexible Motherboard Guidelines for the Intel® Itanium® Processor 9500 Series

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    • 2.6.3 Intel® Itanium® Processor 9300 Series Uncore, Core, and Cache Tolerances

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    • 2.6.4 Intel® Itanium® Processor 9500 Series Uncore and Core Tolerances

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    • 2.6.5 Overshoot and Undershoot Guidelines

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    • 2.6.6 Signal DC Specifications

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    • 2.6.7 Motherboard-Socket Specification for VR Sense Point

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  • 2.7 Core and Uncore Voltage Identification

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    • 2.7.1 Core and Uncore Voltage Identification for the Intel® Itanium® Processor 9300 Series

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    • 2.7.2 Core and Uncore Voltage Identification for the Intel® Itanium® Processor 9500 Series

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  • 2.8 Cache Voltage Identification (Intel® Itanium® Processor 9300 Series only)

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  • 2.9 RSVD, Unused, and DEBUG Pins

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  • 2.10 Mixing Processors

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  • 2.11 Supported Power-up Voltage Sequence

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    • 2.11.1 Supported Power-up Voltage Sequence for the Intel® Itanium® Processor 9300 Series

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    • 2.11.2 Supported Power-up Voltage Sequence for the Intel® Itanium® Processor 9500 Series

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    • 2.11.3 Power-up Voltage Sequence Timing Requirements

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  • 2.12 Supported Power-down Voltage Sequence

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  • 2.13 Timing Relationship Between RESET_N and SKTID

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  • 2.14 Test Access Port (TAP) Connection

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• 3 Pin Listing

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  • 3.1 Processor Package Bottom Pin Assignments

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    • 3.1.1 Package Bottom Pin Listing by Pin Name

      73
    • 3.1.2 Pin Listing by Pin Number

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  • 3.2 Processor Package Top Pin Assignments

    105
    • 3.2.1 Top-Side J1 Connector Two-Dimensional Table

      105
    • 3.2.2 Top-Side J2 Connector Two-Dimensional Table

      108
    • 3.2.3 Top-Side J3 Connector Two-Dimensional Table

      111
    • 3.2.4 Top-Side J4 Connector Two-Dimensional Table

      114
• 4 Mechanical Specifications

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  • 4.1 Package Mechanical Drawing

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  • 4.2 Intel® Itanium® Processor 9300 Series

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  • 4.3 Processor Component Keepout Zones

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  • 4.4 Package Loading Specifications

    129
  • 4.5 Package Handling Guidelines

    129
  • 4.6 Processor Mass Specifications

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  • 4.7 Processor Materials

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  • 4.8 Package Markings

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• 5 Thermal Specifications

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  • 5.1 Thermal Features

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    • 5.1.1 Digital Thermometer

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    • 5.1.2 Thermal Management

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    • 5.1.3 Thermal Alert

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    • 5.1.4 TCONTROL

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    • 5.1.5 Thermal Warning

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    • 5.1.6 Thermal Trip

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    • 5.1.7 PROCHOT

      138
    • 5.1.8 FORCEPR_N Signal Pin

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    • 5.1.9 Ararat Voltage Regulator Thermal Signals

      138
  • 5.2 Package Thermal Specifications and Considerations

    139
  • 5.3 Storage Conditions Specifications

    140
• 6 System Management Bus Interface

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  • 6.1 Introduction

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  • 6.2 SMBus Memory Component

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    • 6.2.1 Processor Information ROM (PIROM)

      144
    • 6.2.2 Scratch EEPROM

      149
    • 6.2.3 PIROM and Scratch EEPROM Supported SMBus Transactions

      150
  • 6.3 Memory Component Addressing

    150
  • 6.4 PIROM Field Definitions

    152
    • 6.4.1 General

      152
    • 6.4.2 Processor Data

      152
    • 6.4.3 Processor Core Data

      152
    • 6.4.4 Processor Uncore Data

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    • 6.4.5 Cache Data

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    • 6.4.6 Package Data

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    • 6.4.7 Part Number Data

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    • 6.4.8 Thermal Reference Data

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    • 6.4.9 Feature Data

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    • 6.4.10 Other Data

      157
    • 6.4.11 Checksums

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• 7 Signal Definitions

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