Intel Core 2 Extreme QX9300 사용자 매뉴얼

차례

• Contents

  3
  • Figures

    4
  • Tables

    4
• 1 Introduction

  7
  • 1.1 Terminology

    7
  • 1.2 References

    9
    • Table 1. References

      9
• 2 Low Power Features

  11
  • 2.1 Clock Control and Low Power States

    11
    • Figure 1. Core Low Power States

      12
    • Figure 2. Package Low Power States

      13
    • Table 2. Coordination of Core Low Power States at the Package Level

      13
    • 2.1.1 Core Low Power State Descriptions

      13
      • 2.1.1.1 Core C0 State

        13
      • 2.1.1.2 Core C1/AutoHALT Powerdown State

        13
      • 2.1.1.3 Core C1/MWAIT Powerdown State

        14
      • 2.1.1.4 Core C2 State

        14
      • 2.1.1.5 Core C3 State

        14
      • 2.1.1.6 Core C4 State

        14
    • 2.1.2 Package Low Power State Descriptions

      14
      • 2.1.2.1 Normal State

        14
      • 2.1.2.2 Stop-Grant State

        15
      • 2.1.2.3 Stop-Grant Snoop State

        15
      • 2.1.2.4 Sleep State

        15
      • 2.1.2.5 Deep Sleep State

        16
      • 2.1.2.6 Deeper Sleep State

        16
  • 2.2 Enhanced Intel SpeedStep® Technology

    17
  • 2.3 Extended Low Power States

    17
  • 2.4 FSB Low Power Enhancements

    18
    • 2.4.1 Dual Intel Dynamic Acceleration

      19
  • 2.5 Processor Power Status Indicator (PSI-2) Signal

    19
    • Figure 3. PSI-2 Functionality Logic Diagram

      19
• 3 Electrical Specifications

  21
  • 3.1 Power and Ground Pins

    21
  • 3.2 Decoupling Guidelines

    21
    • 3.2.1 VCC Decoupling

      21
    • 3.2.2 FSB AGTL+ Decoupling

      21
    • 3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking

      21
  • 3.3 Voltage Identification and Power Sequencing

    22
    • Table 3. Voltage Identification Definition (Sheet 1 of 4)

      23
  • 3.4 Catastrophic Thermal Protection

    26
  • 3.5 Reserved and Unused Pins

    26
  • 3.6 FSB Frequency Select Signals (BSEL[2:0])

    27
    • Table 4. BSEL[2:0] Encoding for BCLK Frequency

      27
  • 3.7 FSB Signal Groups

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    • Table 5. FSB Pin Groups

      28
  • 3.8 CMOS Signals

    29
  • 3.9 Maximum Ratings

    29
    • Table 6. Processor Absolute Maximum Ratings

      29
  • 3.10 Processor DC Specifications

    30
    • Table 7. Voltage and Current Specifications for the Quad-Core Extreme Mobile Processors (Sheet 1 of 2)

      30
    • Table 8. Voltage and Current Specifications for the Quad-Core Mobile Processors (Sheet 1 of 2)

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      • Figure 4. Active VCC and ICC Loadline for Quad-Core Extreme Mobile Processor

        33
      • Figure 5. Deeper Sleep VCC and ICC Loadline for Quad-Core Extreme Mobile Processor

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    • Table 9. AGTL+ Signal Group DC Specifications (Sheet 1 of 2)

      34
    • Table 10. CMOS Signal Group DC Specifications

      36
    • Table 11. Open Drain Signal Group DC Specifications

      36
• 4 Package Mechanical Specifications and Pin Information

  37
  • 4.1 Package Mechanical Specifications

    37
    • Figure 6. Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 1 of 2)

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    • Figure 7. Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 2 of 2)

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  • 4.2 Processor Pinout and Pin List

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    • Figure 8. Quad-Core Processor Pinout (Top Package View, Left Side)

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    • Figure 9. Quad-Core Processor Pinout (Top Package View, Right Side)

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    • Table 12. Pin Listing by Pin Name

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    • Table 13. Pin Listing by Pin Number

      49
    • Table 14. Signal Description (Sheet 1 of 9)

      57
    • Table 15. New Pins for the Quad-Core Mobile Processor

      66
• 5 Thermal Specifications and Design Considerations

  67
  • Table 16. Processor Power Specifications

    67
  • 5.1 Monitoring Die Temperature

    68
    • 5.1.1 Thermal Diode

      68
      • Table 17. Thermal Diode Interface

        69
      • Table 18. Thermal Diode Parameters Using Transistor Model

        69
    • 5.1.2 Intel® Thermal Monitor

      69
    • 5.1.3 Digital Thermal Sensor

      71
  • 5.2 PROCHOT# Signal Pin

    72