Intel III Xeon 933 MHz 사용자 매뉴얼

차례

• 1. INTRODUCTION

  6
• 2. TERMINOLOGY

  7
• 2.1 S.E.C. CARTRIDGE TERMINOLOGY

  7
• REFERENCES

  8
• 3. ELECTRICAL SPECIFICATIONS

  9
• SYSTEM BUS AND VREF

  9
• POWER AND GROUND PINS

  9
• DECOUPLING GUIDELINES

  10
• 3.3.1 VCC_CORE

  10
• LEVEL 2 CACHE DECOUPLING

  10
• SYSTEM BUS AGTL+ DECOUPLING

  10
• CLOCK FREQUENCIES AND SYSTEM BUS CLOCK RATIOS

  10
• MIXING PROCESSORS OF DIFFERENT FREQUENCIES

  12
• VOLTAGE IDENTIFICATION

  12
• SYSTEM BUS UNUSED PINS AND TEST PINS

  14
• SYSTEM BUS SIGNAL GROUPS

  14
• ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS

  15
• A CCESS PORT (TAP) CONNECTION

  15
• M AXIMUM RATINGS

  16
• PROCESSOR DC SPECIFICATIONS

  16
• AGTL+ SYSTEM BUS SPECIFICATIONS

  21
• SYSTEM BUS AC SPECIFICATIONS

  22
• 4. SIGNAL QUALITY

  31
• 4.1 BUS CLOCK SIGNAL QUALITY SPECIFICATIONS

  31
• AGTL+ SIGNAL QUALITY SPECIFICATIONS

  31
• 4.2.1 AGTL+ Ringback Tolerance Specifications

  32
• AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES

  32
• 4.3 NON-GTL+ SIGNAL QUALITY SPECIFICATIONS

  35
• 4.3.1 2.5V Signal Overshoot/Undershoot Guidelines

  36
• 4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications

  36
• 4.3.3 Measuring BCLK Overshoot/Undershoot

  37
• 4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION

  37
• 4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE

  38
• 5. PROCESSOR FEATURES

  39
• 5.1 LOW POWER STATES AND CLOCK CONTROL

  39
• NORMAL STATE — STATE 1

  39
• AUTO HALT POWER DOWN STATE — STATE 2

  39
• STOP-GRANT STATE — STATE 3

  40
• HALT/GRANT SNOOP STATE — STATE 4

  40
• SLEEP STATE — STATE 5

  41
• CLOCK CONTROL

  41
• SYSTEM M ANAGEMENT BUS (SMBUS) INTERFACE

  41
• 5.2.1 PROCESSOR INFORMATION ROM

  42
• SCRATCH EEPROM

  46
• TRANSACTIONS

  46
• THERMAL SENSOR

  47
• THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS

  48
• THERMAL SENSOR REGISTERS

  49
• SMBus Device Addressing

  51
• 6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS

  53
• THERMAL SPECIFICATIONS

  53
• POWER DISSIPATION

  53
• PLATE FLATNESS SPECIFICATION

  55
• PROCESSOR THERMAL ANALYSIS

  55
• THERMAL SOLUTION PERFORMANCE

  55
• THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE

  56
• MEASUREMENTS FOR THERMAL SPECIFICATIONS

  57
• 7. MECHANICAL SPECIFICATIONS

  58
• 7.1 W EIGHT

  62
• 7.2 CARTRIDGE TO CONNECTOR M ATING DETAILS

  62
• 7.3 SUBSTRATE EDGE FINGER SIGNAL LISTING

  64
• 8. INTEGRATION TOOLS

  74
• 8.1 IN -TARGET PROBE (ITP)

  74
• 8.1.1 PRIMARY FUNCTION

  74
• 8.1.2 DEBUG PORT CONNECTOR DESCRIPTION

  74
• 8.1.3 KEEP OUT CONCERNS

  75
• 8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS

  75
• 8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS

  76
• 8.1.6 DEBUG PORT SIGNAL NOTES

  78
• 8.1.7 Using the TAP to Communicate to the processor

  80
• 8.2 LOGIC A NALYZER INTERCONNECT (LAI) AND TRACE CAPTURE TOOL CONSIDERATIONS

  81
• 8.2.1 LAI and Trace Capture Tool System Design Considerations

  81
• 8.2.1 LAI and Trace Capture tool Mechanical Keep Outs

  81
• 9. BOXED PROCESSOR SPECIFICATIONS

  82
• 9.1 INTRODUCTION

  82
• 9.2 M ECHANICAL SPECIFICATIONS

  82
• 9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS

  84
• 9.2.2 BOXED PROCESSOR HEATSINK WEIGHT

  84
• 9.2.3 BOXED PROCESSOR RETENTION MECHANISM

  84
• 9.3 THERMAL SPECIFICATIONS

  85
• 9.3.1 Boxed Processor Cooling Requirements

  85
• 9.3.2 Boxed Processor Passive Heatsink Performance

  85
• 9.3.2 Optional auxiliary fan attachment

  86
• 10. APPENDIX

  89
• 10.1 A LPHABETICAL SIGNALS REFERENCE

  89
• 10.1.1 A[35:03]# (I/O)

  89
• 10.1.2 A20M# (I)

  89
• 10.1.3 ADS# (I/O)

  89
• 10.1.4 AERR# (I/O)

  89
• 10.1.5 AP[1:0]# (I/O)

  89
• 10.1.6 BCLK (I)

  90
• 10.1.7 BERR# (I/O)

  90
• 10.1.8 BINIT# (I/O)

  90
• 10.1.9 BNR# (I/O)

  90
• 10.1.10 BP[3:2]# (I/O)

  90
• 10.1.11 BPM[1:0]# (I/O)

  90
• 10.1.12 BPRI# (I)

  90
• 10.1.13 BR0# (I/O), BR[3:1]# (I)

  90
• 10.1.14 BR0# (I/O), BR[3:1]# (I)

  91
• 10.1.15 CORE_AN_SENSE (O)

  92
• 10.1.16 D[63:00]# (I/O)

  92
• 10.1.17 DBSY# (I/O)

  92
• 10.1.18 DEFER# (I)

  92
• 10.1.19 DEP[7:0]# (I/O)

  92
• 10.1.20 DRDY# (I/O)

  92
• 10.1.21 FERR# (O)

  93
• 10.1.22 FLUSH# (I)

  93
• 10.1.23 HIT# (I/O), HITM# (I/O)

  93
• 10.1.24 HV_EN# (O)

  93
• 10.1.25 IERR# (O)

  93
• 10.1.26 IGNNE# (I)

  93
• 10.1.27 INIT# (I)

  93
• 10.1.28 INTR - see LINT[0]

  94
• 10.1.29 LINT[1:0] (I)

  94
• 10.1.30 LOCK# (I/O)

  94
• 10.1.31 L2_SENSE

  94
• 10.1.32 OCVR_EN (I)

  94
• 10.1.33 OCVR_OK(O)

  94
• 10.1.34 NMI - See LINT[1]

  94
• 10.1.35 PICCLK (I)

  94
• 10.1.36 PICD[1:0] (I/O)

  95
• 10.1.37 PRDY# (O)

  95
• 10.1.38 PREQ# (I)

  95
• 10.1.39 PWREN[1:0] (I)

  95
• 10.1.40 PWRGOOD (I)

  95
• 10.1.41 REQ[4:0]# (I/O)

  97
• 10.1.42 RESET# (I)

  97
• 10.1.43 RP# (I/O)

  97
• 10.1.44 RS[2:0]# (I)

  97
• 10.1.45 RSP# (I)

  98
• 10.1.46 SA[2:0] (I)

  98
• 10.1.47 SELFSB0 (I) SELFSB1 (O)

  98
• 10.1.48 SLP# (I)

  99
• 10.1.49 SMBALERT# (O)

  99
• 10.1.50 SMBCLK (I)

  99
• 10.1.51 SMBDAT (I/O)

  99
• 10.1.52 SMI# (I)

  99
• 10.1.53 STPCLK# (I)

  99
• 10.1.54 TCK (I)

  100
• 10.1.55 TDI (I)

  100
• 10.1.56 TDO (O)

  100
• 10.1.57 TEST_2.5_[A23, A62, B27] (I)

  100
• 10.1.58 THERMTRIP# (O)

  100
• 10.1.59 TMS (I)

  100
• 10.1.60 TRDY# (I)

  100
• 10.1.61 TRST# (I)

  100
• 10.1.62 VID_L2[4:0], VID_CORE[4:0] (O)

  100
• 10.1.63 VIN_SENSE

  101
• 10.1.64 WP (I)

  101