사용자 설명서 (RH80532GC025512)차례Legal - Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel'...2Legal - Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage an...2Legal - Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms...2Legal - Intel may make changes to specifications and product descriptions at any time, without notice.2Legal - Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incomp...2Legal - The Mobile Intel Pentium 4 Processor-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.2Legal - Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.2Legal - Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s Website at http://www.intel.com2Legal - Copyright © Intel Corporation 2000-2003.2Legal - Intel, Pentium, Intel NetBurst, and SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries.2Legal - * Other brands and names are the property of their respective owners.202_TOCHead - Contents301_LevelTOC - 1. Introduction 9301_LevelTOC - 2. Electrical Specifications 13301_LevelTOC - 3. System Bus Signal Quality Specifications 51301_LevelTOC - 4. Package Mechanical Specifications 61301_LevelTOC - 5. Pin Listing and Signal Definitions 67301_LevelTOC - 6. Thermal Specifications and Design Considerations 89301_LevelTOC - 7. Configuration and Low Power Features 93401_LevelTOC - 8. Debug Tools Specifications 97401_LevelTOC -403_TOCHead - Figures503_TOCHead - Tables603_TOCHead - Revision History8Title - Mobile Intel‚ Pentium‚ 4 Processor-M1DocType - Datasheet1Date -1Date - June 20031Date -101_Level - 1. Introduction902_Level - 1.1 Terminology1102_Level - 1.2 References1106_Table - Table 1. References1101_Level - 2. Electrical Specifications1302_Level - 2.1 System Bus and GTLREF1302_Level - 2.2 Power and Ground Pins1302_Level - 2.3 Decoupling Guidelines1303_Level - 2.3.1 VCC Decoupling1403_Level - 2.3.2 System Bus AGTL+ Decoupling1403_Level - 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking1406_Table - Table 2. Core Frequency to System Bus Multipliers14TableNotes - NOTES:14TableStep1 - 1. Ratio is used for debug purposes only.14TableStepn - 2. Listed frequencies are not necessarily committed production frequencies.1502_Level - 2.4 Voltage Identification and Power Sequencing1505_Figure - Figure 1. VCCVID Pin Voltage and Current Requirements1506_Table - Table 3. Voltage Identification Definition1603_Level - 2.4.1 Enhanced Intel® SpeedStep® Technology1603_Level - 2.4.2 Phase Lock Loop (PLL) Power and Filter1705_Figure - Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution17Footnote - .1805_Figure - Figure 3. Phase Lock Loop (PLL) Filter Requirements18TableNotes - NOTES:18TableStep1 - 1. Diagram not to scale.18TableStep1 - 2. No specification for frequencies beyond fcore (core frequency).18TableStep1 - 3. fpeak, if existent, should be less than 0.05 MHz.1803_Level - 2.4.3 Catastrophic Thermal Protection1802_Level - 2.5 Signal Terminations, Unused Pins and TESTHI[10:0]18Step1 - 1. TESTHI[1:0]19Stepn - 2. TESTHI[5:2]19Stepn - 3. TESTHI[10:8]1902_Level - 2.6 System Bus Signal Groups2006_Table - Table 4. System Bus Pin Groups21TableNotes - NOTES:21TableStep1 - 1. Refer to Section 5.2 for signal descriptions.21TableStepn - 2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements.21TableStepn - 3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.21TableStepn - 4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must be terminated on the system board. Refer to Section 2.5 and the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845...21TableStepn - 5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 7.1 for details.2102_Level - 2.7 Asynchronous GTL+ Signals2202_Level - 2.8 Test Access Port (TAP) Connection2202_Level - 2.9 System Bus Frequency Select Signals (BSEL[1:0])2206_Table - Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]2202_Level - 2.10 Maximum Ratings2306_Table - Table 6. Processor DC Absolute Maximum Ratings23TableNotes - NOTES:23TableStep1 - 1. This rating applies to any processor pin.23TableStepn - 2. Contact Intel for storage requirements in excess of one year.2302_Level - 2.11 Processor DC Specifications2306_Table - Table 7. Voltage and Current Specifications24TableNotes - NOTES:24TableStep1 - 1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements available at the time of publication.24TableStepn - 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 and Table 3 for more information. The VID bits will set the typical VCC with...24TableStepn - 3. The voltage specification requirements are measured at the system board socket ball with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MW minimum impedance. The maximum length of ground wire on the ...24TableStepn - 4. Refer to Table 8 to Table 11 and Figure 4 to Figure 6 for the minimum, typical, and maximum VCC (measured at the system board socket ball) allowed for a given current. The processor should not be subjected to any VCC and ICC c...24TableStepn - 5. VCC_MIN is defined at ICC_MAX.24TableStepn - 6. The current specified is also for AutoHALT State.24TableStepn - 7. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification shown in Table 8 to Table 11.24TableStepn - 8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor.24TableStepn - 9. Maximum specifications for ICC Core, ICC Stop-Grant, ICC Sleep, and ICC Deep Sleep are specified at VCC Static Max. derived from the tolerances in Table 8 through Table 11, TJ Max., and under maximum signal loading conditions.24TableStepn - 10. The specification is defined per PLL pin.25TableStepn - 11. The voltage response to a processor current load step (transient) must stay within the Transient Voltage Tolerance Window. The voltage surge or droop response measured in this window is typically on the order of several hundr...25TableStepn - 12. This specification applies to both static and transient components. The rising edge of VCCVID must be monotonic from 0 to 1.1 V. See Figure 1 for current requirements. In this case, monotonic is defined as continuously increa...2506_Table - Table 8. IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode)2505_Figure - Figure 4. Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)2606_Table - Table 9. IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery Optimized Mode)2705_Figure - Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)2806_Table - Table 10. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum Performance Mode (VID = 1.30 V, VID Offset = 4.62%)2806_Table - Table 11. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode (VID = 1.20 V, VID Offset = 4.62%)2905_Figure - Figure 6. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V)2906_Table - Table 12. System Bus Differential BCLK Specifications30TableNotes - NOTES:30TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.30TableStepn - 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.30TableStepn - 3. VHavg is the statistical average of the VH measured by the oscilloscope .30TableStepn - 4. Overshoot is defined as the absolute value of the maximum voltage.30TableStepn - 5. Undershoot is defined as the absolute value of the minimum voltage.30TableStepn - 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback.30TableStepn - 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis.30TableStepn - 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.30TableStepn - 9. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.30TableStepn - 10. DVCROSS is defined as the total variation of all crossing voltages as defined in note 2.3006_Table - Table 13. AGTL+ Signal Group DC Specifications31TableNotes - NOTES:31TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.31TableStepn - 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.31TableStepn - 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.31TableStepn - 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3.31TableStepn - 5. Refer to processor I/O Buffer Models for I/V characteristics.31TableStepn - 6. The VCC referred to in these specifications is the instantaneous VCC.31TableStepn - 7. Vol max of 0.450 Volts is guaranteed when driving into a test load of 50 W as indicated in Figure 8.31TableStepn - 8. Leakage to VSS with pin held at VCC.31TableStepn - 9. Leakage to VCC with pin held at 300 mV.3106_Table - Table 14. Asynchronous GTL+ Signal Group DC Specifications32TableNotes - NOTES:32TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.32TableStepn - 2. All outputs are open-drain.32TableStepn - 3. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3.32TableStepn - 4. The VCC referred to in these specifications refers to instantaneous VCC.32TableStepn - 5. This specification applies to the asynchronous GTL+ signal group.32TableStepn - 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in Figure 8.32TableStepn - 7. Refer to the processor I/O Buffer Models for I/V characteristics.32TableStepn - 8. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50 W as indicated in Figure 8 for the Asynchronous GTL+ signals.32TableStepn - 9. Leakage to VSS with pin held at VCC.32TableStepn - 10. Leakage to VCC with pin held at 300 mV.3206_Table - Table 15. PWRGOOD and TAP Signal Group DC Specifications33TableNotes - NOTES:33TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.33TableStepn - 2. All outputs are open-drain.33TableStepn - 3. TAP signal group must comply with the signal quality specifications in Section 3.33TableStepn - 4. Refer to I/O Buffer Models for I/V characteristics.33TableStepn - 5. The VCC referred to in these specifications refers to instantaneous VCC.33TableStepn - 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown if Figure 8.33TableStepn - 7. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50 Ohms as indicated in Figure 8 for the TAP Signals.33TableStepn - 8. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc for all TAP inputs.33TableStepn - 9. Leakage to VSS with pin held at VCC.33TableStepn - 10. Leakage to VCC with pin held at 300 mV.3306_Table - Table 16. ITPCLKOUT[1:0] DC Specifications33TableNotes - NOTES:33TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.33TableStepn - 2. These parameters are not tested and are based on design simulations.33TableStepn - 3. See Figure 7 for ITPCLKOUT[1:0] output buffer diagram.3305_Figure - Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram34TableNotes - NOTES:34TableStep1 - 1. See Table 16 for range of Ron.34TableStepn - 2. The Vcc referred to in this figure is the instantaneous Vcc.34TableStepn - 3. Refer to the appropriate platform design guidelines for the value of Rext.3406_Table - Table 17. BSEL [1:0] and VID[4:0] DC Specifications34TableNotes - NOTES:34TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.34TableStepn - 2. These parameters are not tested and are based on design simulations.34TableStepn - 3. Leakage to Vss with pin held at 2.50 V.3402_Level - 2.12 AGTL+ System Bus Specifications3406_Table - Table 18. AGTL+ Bus Voltage Definitions35TableNotes - NOTES:35TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.35TableStep1 - 2. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of VCC.35TableStep1 - 3. GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors or 1% tolerance matched resistors. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for i...35TableStep1 - 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O buffer models for I/V characteristics.35TableStep1 - 5. COMP resistance must be provided on the system board with 1% tolerance resistors. See the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for implementation details.35TableStep1 - 6. The VCC referred to in these specifications is the instantaneous VCC.3502_Level - 2.13 System Bus AC Specifications3506_Table - Table 19. System Bus Differential Clock Specifications36TableNotes - NOTES:36TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.36TableStep1 - 2. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2).36TableStep1 - 3. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability.36TableStep1 - 4. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).3606_Table - Table 20. System Bus Common Clock AC Specifications36TableNotes - NOTES:36TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.36TableStep1 - 2. Not 100% tested. Specified by design characterization.36TableStep1 - 3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.36TableStep1 - 4. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC ± 2%.36TableStep1 - 5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.4 V/ns to 4.0 V/ns.36TableStep1 - 6. RESET# can be asserted asynchronously, but must be deasserted synchronously.36TableStep1 - 7. This should be measured after VCC and BCLK[1:0] become stable.36TableStep1 - 8. Maximum specification applies only while PWRGOOD is asserted.3606_Table - Table 21. System Bus Source Synch AC Specifications AGTL+ Signal Group37TableNotes - NOTES:37TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.37TableStepn - 2. Not 100% tested. Specified by design characterization.37TableStepn - 3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are ...37TableStepn - 4. Unless otherwise noted these specifications apply to both data and address timings.37TableStepn - 5. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC ± 2%.37TableStepn - 6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.3 V/ns to 4.0V /ns.37TableStepn - 7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe.37TableStepn - 8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for more information on...37TableStepn - 9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for more information on ...37TableStepn - 10. The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of ADSTB#.37TableStepn - 11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.37TableStepn - 12. The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK period (...37TableStepn - 13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.3706_Table - Table 22. Miscellaneous Signals AC Specifications38TableNotes - NOTES:38TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.38TableStepn - 2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge at 0.5*VCC38TableStepn - 3. These signals may be driven asynchronously.38TableStepn - 4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.38TableStepn - 5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion and before the deassertion of PROCHOT# for the processor to complete current instruction execution. This spe...38TableStepn - 6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.3806_Table - Table 23. System Bus AC Specifications (Reset Conditions)38TableNotes - NOTES:38TableStep1 - 1. Before the deassertion of RESET#.38TableStepn - 2. After clock that deasserts RESET#.3806_Table - Table 24. TAP Signals AC Specifications39TableNotes - NOTES:39TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.39TableStepn - 2. Not 100% tested. Specified by design characterization.39TableStepn - 3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins.39TableStepn - 4. Rise and fall times are measured from the 20% to 80% points of the signal swing.39TableStepn - 5. Referenced to the rising edge of TCK.39TableStepn - 6. Referenced to the falling edge of TCK.39TableStepn - 7. Specifications for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of 0.5 V/ns39TableStepn - 8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.39TableStepn - 9. It is recommended that TMS be asserted while TRST# is being deasserted.3906_Table - Table 25. ITPCLKOUT[1:0] AC Specifications39TableNotes - NOTES:39TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.39TableStepn - 2. These parameters are not tested and are based on design simulations.39TableStepn - 3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.3906_Table - Table 26. Stop Grant/Sleep/Deep Sleep/Enhanced Intel SpeedStep Technology AC Specifications40TableNotes - NOTES:40TableStep1 - 1. Input signals other than RESET# must be held constant in the Sleep state.40TableStep1 - 2. The BCLK can be stopped after DPSLP# is asserted. The BCLK must be turned on and within specification before DPSLP# is deasserted.4002_Level - 2.14 Processor AC Timing Waveforms40TableNotes - NOTES:40TableStep1 - 1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.40TableStep1 - 2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Sou...40TableStep1 - 3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+ strobe signal timings are referenced at GTLREF at the processor core silicon.40TableStep1 - 4. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.5*VCC at the processor pins.4005_Figure - Figure 8. AC Test Circuit4105_Figure - Figure 9. TCK Clock Waveform4105_Figure - Figure 10. Differential Clock Waveform4205_Figure - Figure 11. Differential Clock Crosspoint Specification4305_Figure - Figure 12. System Bus Common Clock Valid Delay Timings4305_Figure - Figure 13. System Bus Reset and Configuration Timings4405_Figure - Figure 14. Source Synchronous 2X (Address) Timings4405_Figure - Figure 15. Source Synchronous 4X Timings4505_Figure - Figure 16. Power Up Sequence4605_Figure - Figure 17. Power Down Sequence4605_Figure - Figure 18. Test Reset Timings4705_Figure - Figure 19. THERMTRIP# to Vcc Timing4705_Figure - Figure 20. FERR#/PBE# Valid Delay Timing4705_Figure - Figure 21. TAP Valid Delay Timing4805_Figure - Figure 22. ITPCLKOUT Valid Delay Timing4805_Figure - Figure 23. Stop Grant/Sleep/Deep Sleep Timing4905_Figure - Figure 24. Enhanced Intel SpeedStep Technology/Deep Sleep Timing5001_Level - 3. System Bus Signal Quality Specifications5102_Level - 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines5106_Table - Table 27. BCLK Signal Quality Specifications51TableNotes - NOTES:51TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.51TableStep1 - 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specific...5105_Figure - Figure 25. BCLK Signal Integrity Waveform5202_Level - 3.2 System Bus Signal Quality Specifications and Measurement Guidelines5206_Table - Table 28. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups52TableNotes - NOTES:52TableStep1 - 1. All signal integrity specifications are measured at the processor silicon (pads).52TableStep1 - 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.52TableStep1 - 3. Specifications are for the edge rate of 0.3 - 4.0 V/ns.52TableStep1 - 4. All values specified by design characterization.52TableStep1 - 5. Please see Section 3.3 for maximum allowable overshoot.52TableStep1 - 6. Ringback between GTLREF + 10% and GTLREF - 10% is not supported.52TableStep1 - 7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other sources of system noise.5206_Table - Table 29. Ringback Specifications for PWRGOOD Input and TAP Signal Groups53TableNotes - NOTES:53TableStep1 - 1. All signal integrity specifications are measured at the processor silicon.53TableStepn - 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.53TableStepn - 3. Please see Section 3.3 for maximum allowable overshoot.53TableStepn - 4. Please see Section 2.11 for the DC specifications.5305_Figure - Figure 26. Low-to-High System Bus Receiver Ringback Tolerance5305_Figure - Figure 27. High-to-Low System Bus Receiver Ringback Tolerance5305_Figure - Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers5405_Figure - Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers5402_Level - 3.3 System Bus Signal Quality Specifications and Measurement Guidelines5503_Level - 3.3.1 Overshoot/Undershoot Guidelines5503_Level - 3.3.2 Overshoot/Undershoot Magnitude5503_Level - 3.3.3 Overshoot/Undershoot Pulse Duration55Note - Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration.5603_Level - 3.3.4 Activity Factor56Note - Note: 1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency.56Note - Note: 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#.56Note - Note: 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#.5603_Level - 3.3.5 Reading Overshoot/Undershoot Specification Tables56Step1 - 1. Determine the signal group a particular signal falls into. If the signal is an AGTL+ signal operating in the common clock domain, use Table 32. For AGTL+ signals operating in the 2x source synchronous domain, use Table 31. For AGTL...56Stepn - 2. Determine the magnitude of the overshoot (relative to VSS).56Stepn - 3. Determine the activity factor (how often does this overshoot occur?)56Stepn - 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed.56Stepn - 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications.5603_Level - 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications57Step1 - 1. Ensure no signal ever exceeds VCC or -0.25 V OR57Stepn - 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables OR57Stepn - 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst case overshoot or undershoot events...57TableNotes - NOTES:57TableStep1 - 1. Absolute Maximum Overshoot magnitude of 1.70 V must never be exceeded.57TableStepn - 2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative to VCC.57TableStepn - 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS.57TableStepn - 4. Ringback below VCC can not be subtracted from overshoots/undershoots.57TableStepn - 5. Lesser undershoot does not allocate longer or larger overshoot.57TableStepn - 6. OEM's are strongly encouraged to follow Intel provided layout guidelines.57TableStepn - 7. All values specified by design characterization.5706_Table - Table 30. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance57TableNotes - NOTES:57TableStep1 - 1. These specifications are measured at the processor core silicon.57TableStepn - 2. BCLK period is 10 ns.5706_Table - Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance58TableNotes - NOTES:58TableStep1 - 1. These specifications are measured at the processor core silicon.58TableStepn - 2. BCLK period is 10 ns.5806_Table - Table 32. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance58TableNotes - NOTES:58TableStep1 - 1. These specifications are measured at the processor core silicon.58TableStepn - 2. BCLK period is 10 ns.5806_Table - Table 33. Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/ Undershoot Tolerance59TableNotes - NOTES:59TableStep1 - 1. These specifications are measured at the processor core silicon.59TableStepn - 2. BCLK period is 10 ns.5905_Figure - Figure 30. Maximum Acceptable Overshoot/Undershoot Waveform5901_Level - 4. Package Mechanical Specifications6105_Figure - Figure 31. Micro-FCPGA Package Top and Bottom Isometric Views6105_Figure - Figure 32. Micro-FCPGA Package Top and Side View6206_Table - Table 34. Micro-FCPGA Package Dimensions63TableNotes - NOTES:63TableStep1 - 1. All Dimensions are subject to change. Values shown are for reference only.63TableStep1 - 2. Overall height with socket is based on design dimensions of the Micro-FCPGA package and socket with no thermal solution attached. Values were based on design specifications and tolerances. This dimension is subject to change b...6305_Figure - Figure 33. Micro-FCPGA Package - Bottom View6402_Level - 4.1 Processor Pin-Out6405_Figure - Figure 34. The Coordinates of the Processor Pins as Viewed From the Top of the Package.6506_Table - Table 35. Pin Listing by Pin Name6806_Table - Table 36. Pin Listing by Pin Number7401_Level - 5. Pin Listing and Signal Definitions6702_Level - 5.1 Mobile Intel Pentium 4 Processor-M Pin Assignments6702_Level - 5.2 Alphabetical Signals Reference8106_Table - Table 37. Signal Description (Page 8 of 8)8101_Level - 6. Thermal Specifications and Design Considerations8906_Table - Table 38. Power Specifications for the Mobile Intel Pentium 4 Processor-M89TableNotes - NOTES:89TableStep1 - 1. TDP is defined as the worst case power dissipated by the processor while executing publicly available software under normal operating conditions at nominal voltages that meet the load line specifications. The TDP number shown ...89TableStep1 - 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated.90TableStep1 - 3. The maximum junction temperature (TJ) is specified as the hottest location on the die. The thermal monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 6.1.1 for TJ measurement gu...9002_Level - 6.1 Thermal Specifications9003_Level - 6.1.1 Thermal Diode90Note - Note: The reading of the thermal sensor connected to the thermal diode does not reflect the temperature of the hottest location on the die (TJ). This is due to inaccuracies in the thermal diode, on-die temperature gradients between the...9006_Table - Table 39. Thermal Diode Interface9006_Table - Table 40. Thermal Diode Specifications90TableNotes - NOTES:90TableStep1 - 1. Intel does not support or recommend operation of the thermal diode under reverse bias.90TableStepn - 2. Characterized at 100 C.90TableStepn - 3. Not 100% tested. Specified by design characterization.90TableStepn - 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVd/nkT) -1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = ...90TableStepn - 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resi...9103_Level - 6.1.2 Thermal Monitor9101_Level - 7. Configuration and Low Power Features9302_Level - 7.1 Power-On Configuration Options9306_Table - Table 41. Power-On Configuration Option Pins9302_Level - 7.2 Clock Control and Low Power States9303_Level - 7.2.1 Normal State9303_Level - 7.2.2 AutoHALT Powerdown State9305_Figure - Figure 35. Clock Control States9403_Level - 7.2.3 Stop-Grant State9403_Level - 7.2.4 HALT/Grant Snoop State9503_Level - 7.2.5 Sleep State9503_Level - 7.2.6 Deep Sleep State9503_Level - 7.2.7 Deeper Sleep State9602_Level - 7.3 Enhanced Intel SpeedStep Technology9601_Level - 8. Debug Tools Specifications9702_Level - 8.1 Logic Analyzer Interface (LAI)9703_Level - 8.1.1 Mechanical Considerations9703_Level - 8.1.2 Electrical Considerations9701_LevelTOC - 1. Introduction 901_LevelTOC - 2. Electrical Specifications 1301_LevelTOC - 3. System Bus Signal Quality Specifications 5101_LevelTOC - 4. Package Mechanical Specifications 6101_LevelTOC - 5. Pin Listing and Signal Definitions 6701_LevelTOC - 6. Thermal Specifications and Design Considerations 8901_LevelTOC - 7. Configuration and Low Power Features 9301_LevelTOC - 8. Debug Tools Specifications 97크기: 5.19메가바이트페이지: 97Language: English매뉴얼 열기
사용자 설명서 (RH80532GC041512)차례Legal - Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel'...2Legal - Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage an...2Legal - Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms...2Legal - Intel may make changes to specifications and product descriptions at any time, without notice.2Legal - Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incomp...2Legal - The Mobile Intel Pentium 4 Processor-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.2Legal - Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.2Legal - Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s Website at http://www.intel.com2Legal - Copyright © Intel Corporation 2000-2003.2Legal - Intel, Pentium, Intel NetBurst, and SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries.2Legal - * Other brands and names are the property of their respective owners.202_TOCHead - Contents301_LevelTOC - 1. Introduction 9301_LevelTOC - 2. Electrical Specifications 13301_LevelTOC - 3. System Bus Signal Quality Specifications 51301_LevelTOC - 4. Package Mechanical Specifications 61301_LevelTOC - 5. Pin Listing and Signal Definitions 67301_LevelTOC - 6. Thermal Specifications and Design Considerations 89301_LevelTOC - 7. Configuration and Low Power Features 93401_LevelTOC - 8. Debug Tools Specifications 97401_LevelTOC -403_TOCHead - Figures503_TOCHead - Tables603_TOCHead - Revision History8Title - Mobile Intel‚ Pentium‚ 4 Processor-M1DocType - Datasheet1Date -1Date - June 20031Date -101_Level - 1. Introduction902_Level - 1.1 Terminology1102_Level - 1.2 References1106_Table - Table 1. References1101_Level - 2. Electrical Specifications1302_Level - 2.1 System Bus and GTLREF1302_Level - 2.2 Power and Ground Pins1302_Level - 2.3 Decoupling Guidelines1303_Level - 2.3.1 VCC Decoupling1403_Level - 2.3.2 System Bus AGTL+ Decoupling1403_Level - 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking1406_Table - Table 2. Core Frequency to System Bus Multipliers14TableNotes - NOTES:14TableStep1 - 1. Ratio is used for debug purposes only.14TableStepn - 2. Listed frequencies are not necessarily committed production frequencies.1502_Level - 2.4 Voltage Identification and Power Sequencing1505_Figure - Figure 1. VCCVID Pin Voltage and Current Requirements1506_Table - Table 3. Voltage Identification Definition1603_Level - 2.4.1 Enhanced Intel® SpeedStep® Technology1603_Level - 2.4.2 Phase Lock Loop (PLL) Power and Filter1705_Figure - Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution17Footnote - .1805_Figure - Figure 3. Phase Lock Loop (PLL) Filter Requirements18TableNotes - NOTES:18TableStep1 - 1. Diagram not to scale.18TableStep1 - 2. No specification for frequencies beyond fcore (core frequency).18TableStep1 - 3. fpeak, if existent, should be less than 0.05 MHz.1803_Level - 2.4.3 Catastrophic Thermal Protection1802_Level - 2.5 Signal Terminations, Unused Pins and TESTHI[10:0]18Step1 - 1. TESTHI[1:0]19Stepn - 2. TESTHI[5:2]19Stepn - 3. TESTHI[10:8]1902_Level - 2.6 System Bus Signal Groups2006_Table - Table 4. System Bus Pin Groups21TableNotes - NOTES:21TableStep1 - 1. Refer to Section 5.2 for signal descriptions.21TableStepn - 2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements.21TableStepn - 3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.21TableStepn - 4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must be terminated on the system board. Refer to Section 2.5 and the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845...21TableStepn - 5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 7.1 for details.2102_Level - 2.7 Asynchronous GTL+ Signals2202_Level - 2.8 Test Access Port (TAP) Connection2202_Level - 2.9 System Bus Frequency Select Signals (BSEL[1:0])2206_Table - Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]2202_Level - 2.10 Maximum Ratings2306_Table - Table 6. Processor DC Absolute Maximum Ratings23TableNotes - NOTES:23TableStep1 - 1. This rating applies to any processor pin.23TableStepn - 2. Contact Intel for storage requirements in excess of one year.2302_Level - 2.11 Processor DC Specifications2306_Table - Table 7. Voltage and Current Specifications24TableNotes - NOTES:24TableStep1 - 1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements available at the time of publication.24TableStepn - 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 and Table 3 for more information. The VID bits will set the typical VCC with...24TableStepn - 3. The voltage specification requirements are measured at the system board socket ball with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MW minimum impedance. The maximum length of ground wire on the ...24TableStepn - 4. Refer to Table 8 to Table 11 and Figure 4 to Figure 6 for the minimum, typical, and maximum VCC (measured at the system board socket ball) allowed for a given current. The processor should not be subjected to any VCC and ICC c...24TableStepn - 5. VCC_MIN is defined at ICC_MAX.24TableStepn - 6. The current specified is also for AutoHALT State.24TableStepn - 7. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification shown in Table 8 to Table 11.24TableStepn - 8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor.24TableStepn - 9. Maximum specifications for ICC Core, ICC Stop-Grant, ICC Sleep, and ICC Deep Sleep are specified at VCC Static Max. derived from the tolerances in Table 8 through Table 11, TJ Max., and under maximum signal loading conditions.24TableStepn - 10. The specification is defined per PLL pin.25TableStepn - 11. The voltage response to a processor current load step (transient) must stay within the Transient Voltage Tolerance Window. The voltage surge or droop response measured in this window is typically on the order of several hundr...25TableStepn - 12. This specification applies to both static and transient components. The rising edge of VCCVID must be monotonic from 0 to 1.1 V. See Figure 1 for current requirements. In this case, monotonic is defined as continuously increa...2506_Table - Table 8. IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode)2505_Figure - Figure 4. Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)2606_Table - Table 9. IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery Optimized Mode)2705_Figure - Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)2806_Table - Table 10. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum Performance Mode (VID = 1.30 V, VID Offset = 4.62%)2806_Table - Table 11. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode (VID = 1.20 V, VID Offset = 4.62%)2905_Figure - Figure 6. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V)2906_Table - Table 12. System Bus Differential BCLK Specifications30TableNotes - NOTES:30TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.30TableStepn - 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.30TableStepn - 3. VHavg is the statistical average of the VH measured by the oscilloscope .30TableStepn - 4. Overshoot is defined as the absolute value of the maximum voltage.30TableStepn - 5. Undershoot is defined as the absolute value of the minimum voltage.30TableStepn - 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback.30TableStepn - 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis.30TableStepn - 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.30TableStepn - 9. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.30TableStepn - 10. DVCROSS is defined as the total variation of all crossing voltages as defined in note 2.3006_Table - Table 13. AGTL+ Signal Group DC Specifications31TableNotes - NOTES:31TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.31TableStepn - 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.31TableStepn - 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.31TableStepn - 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3.31TableStepn - 5. Refer to processor I/O Buffer Models for I/V characteristics.31TableStepn - 6. The VCC referred to in these specifications is the instantaneous VCC.31TableStepn - 7. Vol max of 0.450 Volts is guaranteed when driving into a test load of 50 W as indicated in Figure 8.31TableStepn - 8. Leakage to VSS with pin held at VCC.31TableStepn - 9. Leakage to VCC with pin held at 300 mV.3106_Table - Table 14. Asynchronous GTL+ Signal Group DC Specifications32TableNotes - NOTES:32TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.32TableStepn - 2. All outputs are open-drain.32TableStepn - 3. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3.32TableStepn - 4. The VCC referred to in these specifications refers to instantaneous VCC.32TableStepn - 5. This specification applies to the asynchronous GTL+ signal group.32TableStepn - 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in Figure 8.32TableStepn - 7. Refer to the processor I/O Buffer Models for I/V characteristics.32TableStepn - 8. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50 W as indicated in Figure 8 for the Asynchronous GTL+ signals.32TableStepn - 9. Leakage to VSS with pin held at VCC.32TableStepn - 10. Leakage to VCC with pin held at 300 mV.3206_Table - Table 15. PWRGOOD and TAP Signal Group DC Specifications33TableNotes - NOTES:33TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.33TableStepn - 2. All outputs are open-drain.33TableStepn - 3. TAP signal group must comply with the signal quality specifications in Section 3.33TableStepn - 4. Refer to I/O Buffer Models for I/V characteristics.33TableStepn - 5. The VCC referred to in these specifications refers to instantaneous VCC.33TableStepn - 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown if Figure 8.33TableStepn - 7. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50 Ohms as indicated in Figure 8 for the TAP Signals.33TableStepn - 8. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc for all TAP inputs.33TableStepn - 9. Leakage to VSS with pin held at VCC.33TableStepn - 10. Leakage to VCC with pin held at 300 mV.3306_Table - Table 16. ITPCLKOUT[1:0] DC Specifications33TableNotes - NOTES:33TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.33TableStepn - 2. These parameters are not tested and are based on design simulations.33TableStepn - 3. See Figure 7 for ITPCLKOUT[1:0] output buffer diagram.3305_Figure - Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram34TableNotes - NOTES:34TableStep1 - 1. See Table 16 for range of Ron.34TableStepn - 2. The Vcc referred to in this figure is the instantaneous Vcc.34TableStepn - 3. Refer to the appropriate platform design guidelines for the value of Rext.3406_Table - Table 17. BSEL [1:0] and VID[4:0] DC Specifications34TableNotes - NOTES:34TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.34TableStepn - 2. These parameters are not tested and are based on design simulations.34TableStepn - 3. Leakage to Vss with pin held at 2.50 V.3402_Level - 2.12 AGTL+ System Bus Specifications3406_Table - Table 18. AGTL+ Bus Voltage Definitions35TableNotes - NOTES:35TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.35TableStep1 - 2. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of VCC.35TableStep1 - 3. GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors or 1% tolerance matched resistors. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for i...35TableStep1 - 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O buffer models for I/V characteristics.35TableStep1 - 5. COMP resistance must be provided on the system board with 1% tolerance resistors. See the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for implementation details.35TableStep1 - 6. The VCC referred to in these specifications is the instantaneous VCC.3502_Level - 2.13 System Bus AC Specifications3506_Table - Table 19. System Bus Differential Clock Specifications36TableNotes - NOTES:36TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.36TableStep1 - 2. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2).36TableStep1 - 3. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability.36TableStep1 - 4. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).3606_Table - Table 20. System Bus Common Clock AC Specifications36TableNotes - NOTES:36TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.36TableStep1 - 2. Not 100% tested. Specified by design characterization.36TableStep1 - 3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.36TableStep1 - 4. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC ± 2%.36TableStep1 - 5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.4 V/ns to 4.0 V/ns.36TableStep1 - 6. RESET# can be asserted asynchronously, but must be deasserted synchronously.36TableStep1 - 7. This should be measured after VCC and BCLK[1:0] become stable.36TableStep1 - 8. Maximum specification applies only while PWRGOOD is asserted.3606_Table - Table 21. System Bus Source Synch AC Specifications AGTL+ Signal Group37TableNotes - NOTES:37TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.37TableStepn - 2. Not 100% tested. Specified by design characterization.37TableStepn - 3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are ...37TableStepn - 4. Unless otherwise noted these specifications apply to both data and address timings.37TableStepn - 5. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC ± 2%.37TableStepn - 6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.3 V/ns to 4.0V /ns.37TableStepn - 7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe.37TableStepn - 8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for more information on...37TableStepn - 9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for more information on ...37TableStepn - 10. The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of ADSTB#.37TableStepn - 11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.37TableStepn - 12. The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK period (...37TableStepn - 13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.3706_Table - Table 22. Miscellaneous Signals AC Specifications38TableNotes - NOTES:38TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.38TableStepn - 2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge at 0.5*VCC38TableStepn - 3. These signals may be driven asynchronously.38TableStepn - 4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.38TableStepn - 5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion and before the deassertion of PROCHOT# for the processor to complete current instruction execution. This spe...38TableStepn - 6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.3806_Table - Table 23. System Bus AC Specifications (Reset Conditions)38TableNotes - NOTES:38TableStep1 - 1. Before the deassertion of RESET#.38TableStepn - 2. After clock that deasserts RESET#.3806_Table - Table 24. TAP Signals AC Specifications39TableNotes - NOTES:39TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.39TableStepn - 2. Not 100% tested. Specified by design characterization.39TableStepn - 3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins.39TableStepn - 4. Rise and fall times are measured from the 20% to 80% points of the signal swing.39TableStepn - 5. Referenced to the rising edge of TCK.39TableStepn - 6. Referenced to the falling edge of TCK.39TableStepn - 7. Specifications for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of 0.5 V/ns39TableStepn - 8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.39TableStepn - 9. It is recommended that TMS be asserted while TRST# is being deasserted.3906_Table - Table 25. ITPCLKOUT[1:0] AC Specifications39TableNotes - NOTES:39TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.39TableStepn - 2. These parameters are not tested and are based on design simulations.39TableStepn - 3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.3906_Table - Table 26. Stop Grant/Sleep/Deep Sleep/Enhanced Intel SpeedStep Technology AC Specifications40TableNotes - NOTES:40TableStep1 - 1. Input signals other than RESET# must be held constant in the Sleep state.40TableStep1 - 2. The BCLK can be stopped after DPSLP# is asserted. The BCLK must be turned on and within specification before DPSLP# is deasserted.4002_Level - 2.14 Processor AC Timing Waveforms40TableNotes - NOTES:40TableStep1 - 1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.40TableStep1 - 2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Sou...40TableStep1 - 3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+ strobe signal timings are referenced at GTLREF at the processor core silicon.40TableStep1 - 4. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.5*VCC at the processor pins.4005_Figure - Figure 8. AC Test Circuit4105_Figure - Figure 9. TCK Clock Waveform4105_Figure - Figure 10. Differential Clock Waveform4205_Figure - Figure 11. Differential Clock Crosspoint Specification4305_Figure - Figure 12. System Bus Common Clock Valid Delay Timings4305_Figure - Figure 13. System Bus Reset and Configuration Timings4405_Figure - Figure 14. Source Synchronous 2X (Address) Timings4405_Figure - Figure 15. Source Synchronous 4X Timings4505_Figure - Figure 16. Power Up Sequence4605_Figure - Figure 17. Power Down Sequence4605_Figure - Figure 18. Test Reset Timings4705_Figure - Figure 19. THERMTRIP# to Vcc Timing4705_Figure - Figure 20. FERR#/PBE# Valid Delay Timing4705_Figure - Figure 21. TAP Valid Delay Timing4805_Figure - Figure 22. ITPCLKOUT Valid Delay Timing4805_Figure - Figure 23. Stop Grant/Sleep/Deep Sleep Timing4905_Figure - Figure 24. Enhanced Intel SpeedStep Technology/Deep Sleep Timing5001_Level - 3. System Bus Signal Quality Specifications5102_Level - 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines5106_Table - Table 27. BCLK Signal Quality Specifications51TableNotes - NOTES:51TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.51TableStep1 - 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specific...5105_Figure - Figure 25. BCLK Signal Integrity Waveform5202_Level - 3.2 System Bus Signal Quality Specifications and Measurement Guidelines5206_Table - Table 28. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups52TableNotes - NOTES:52TableStep1 - 1. All signal integrity specifications are measured at the processor silicon (pads).52TableStep1 - 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.52TableStep1 - 3. Specifications are for the edge rate of 0.3 - 4.0 V/ns.52TableStep1 - 4. All values specified by design characterization.52TableStep1 - 5. Please see Section 3.3 for maximum allowable overshoot.52TableStep1 - 6. Ringback between GTLREF + 10% and GTLREF - 10% is not supported.52TableStep1 - 7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other sources of system noise.5206_Table - Table 29. Ringback Specifications for PWRGOOD Input and TAP Signal Groups53TableNotes - NOTES:53TableStep1 - 1. All signal integrity specifications are measured at the processor silicon.53TableStepn - 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.53TableStepn - 3. Please see Section 3.3 for maximum allowable overshoot.53TableStepn - 4. Please see Section 2.11 for the DC specifications.5305_Figure - Figure 26. Low-to-High System Bus Receiver Ringback Tolerance5305_Figure - Figure 27. High-to-Low System Bus Receiver Ringback Tolerance5305_Figure - Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers5405_Figure - Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers5402_Level - 3.3 System Bus Signal Quality Specifications and Measurement Guidelines5503_Level - 3.3.1 Overshoot/Undershoot Guidelines5503_Level - 3.3.2 Overshoot/Undershoot Magnitude5503_Level - 3.3.3 Overshoot/Undershoot Pulse Duration55Note - Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration.5603_Level - 3.3.4 Activity Factor56Note - Note: 1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency.56Note - Note: 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#.56Note - Note: 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#.5603_Level - 3.3.5 Reading Overshoot/Undershoot Specification Tables56Step1 - 1. Determine the signal group a particular signal falls into. If the signal is an AGTL+ signal operating in the common clock domain, use Table 32. For AGTL+ signals operating in the 2x source synchronous domain, use Table 31. For AGTL...56Stepn - 2. Determine the magnitude of the overshoot (relative to VSS).56Stepn - 3. Determine the activity factor (how often does this overshoot occur?)56Stepn - 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed.56Stepn - 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications.5603_Level - 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications57Step1 - 1. Ensure no signal ever exceeds VCC or -0.25 V OR57Stepn - 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables OR57Stepn - 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst case overshoot or undershoot events...57TableNotes - NOTES:57TableStep1 - 1. Absolute Maximum Overshoot magnitude of 1.70 V must never be exceeded.57TableStepn - 2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative to VCC.57TableStepn - 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS.57TableStepn - 4. Ringback below VCC can not be subtracted from overshoots/undershoots.57TableStepn - 5. Lesser undershoot does not allocate longer or larger overshoot.57TableStepn - 6. OEM's are strongly encouraged to follow Intel provided layout guidelines.57TableStepn - 7. All values specified by design characterization.5706_Table - Table 30. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance57TableNotes - NOTES:57TableStep1 - 1. These specifications are measured at the processor core silicon.57TableStepn - 2. BCLK period is 10 ns.5706_Table - Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance58TableNotes - NOTES:58TableStep1 - 1. These specifications are measured at the processor core silicon.58TableStepn - 2. BCLK period is 10 ns.5806_Table - Table 32. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance58TableNotes - NOTES:58TableStep1 - 1. These specifications are measured at the processor core silicon.58TableStepn - 2. BCLK period is 10 ns.5806_Table - Table 33. Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/ Undershoot Tolerance59TableNotes - NOTES:59TableStep1 - 1. These specifications are measured at the processor core silicon.59TableStepn - 2. BCLK period is 10 ns.5905_Figure - Figure 30. Maximum Acceptable Overshoot/Undershoot Waveform5901_Level - 4. Package Mechanical Specifications6105_Figure - Figure 31. Micro-FCPGA Package Top and Bottom Isometric Views6105_Figure - Figure 32. Micro-FCPGA Package Top and Side View6206_Table - Table 34. Micro-FCPGA Package Dimensions63TableNotes - NOTES:63TableStep1 - 1. All Dimensions are subject to change. Values shown are for reference only.63TableStep1 - 2. Overall height with socket is based on design dimensions of the Micro-FCPGA package and socket with no thermal solution attached. Values were based on design specifications and tolerances. This dimension is subject to change b...6305_Figure - Figure 33. Micro-FCPGA Package - Bottom View6402_Level - 4.1 Processor Pin-Out6405_Figure - Figure 34. The Coordinates of the Processor Pins as Viewed From the Top of the Package.6506_Table - Table 35. Pin Listing by Pin Name6806_Table - Table 36. Pin Listing by Pin Number7401_Level - 5. Pin Listing and Signal Definitions6702_Level - 5.1 Mobile Intel Pentium 4 Processor-M Pin Assignments6702_Level - 5.2 Alphabetical Signals Reference8106_Table - Table 37. Signal Description (Page 8 of 8)8101_Level - 6. Thermal Specifications and Design Considerations8906_Table - Table 38. Power Specifications for the Mobile Intel Pentium 4 Processor-M89TableNotes - NOTES:89TableStep1 - 1. TDP is defined as the worst case power dissipated by the processor while executing publicly available software under normal operating conditions at nominal voltages that meet the load line specifications. The TDP number shown ...89TableStep1 - 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated.90TableStep1 - 3. The maximum junction temperature (TJ) is specified as the hottest location on the die. The thermal monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 6.1.1 for TJ measurement gu...9002_Level - 6.1 Thermal Specifications9003_Level - 6.1.1 Thermal Diode90Note - Note: The reading of the thermal sensor connected to the thermal diode does not reflect the temperature of the hottest location on the die (TJ). This is due to inaccuracies in the thermal diode, on-die temperature gradients between the...9006_Table - Table 39. Thermal Diode Interface9006_Table - Table 40. Thermal Diode Specifications90TableNotes - NOTES:90TableStep1 - 1. Intel does not support or recommend operation of the thermal diode under reverse bias.90TableStepn - 2. Characterized at 100 C.90TableStepn - 3. Not 100% tested. Specified by design characterization.90TableStepn - 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVd/nkT) -1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = ...90TableStepn - 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resi...9103_Level - 6.1.2 Thermal Monitor9101_Level - 7. Configuration and Low Power Features9302_Level - 7.1 Power-On Configuration Options9306_Table - Table 41. Power-On Configuration Option Pins9302_Level - 7.2 Clock Control and Low Power States9303_Level - 7.2.1 Normal State9303_Level - 7.2.2 AutoHALT Powerdown State9305_Figure - Figure 35. Clock Control States9403_Level - 7.2.3 Stop-Grant State9403_Level - 7.2.4 HALT/Grant Snoop State9503_Level - 7.2.5 Sleep State9503_Level - 7.2.6 Deep Sleep State9503_Level - 7.2.7 Deeper Sleep State9602_Level - 7.3 Enhanced Intel SpeedStep Technology9601_Level - 8. Debug Tools Specifications9702_Level - 8.1 Logic Analyzer Interface (LAI)9703_Level - 8.1.1 Mechanical Considerations9703_Level - 8.1.2 Electrical Considerations9701_LevelTOC - 1. Introduction 901_LevelTOC - 2. Electrical Specifications 1301_LevelTOC - 3. System Bus Signal Quality Specifications 5101_LevelTOC - 4. Package Mechanical Specifications 6101_LevelTOC - 5. Pin Listing and Signal Definitions 6701_LevelTOC - 6. Thermal Specifications and Design Considerations 8901_LevelTOC - 7. Configuration and Low Power Features 9301_LevelTOC - 8. Debug Tools Specifications 97크기: 5.19메가바이트페이지: 97Language: English매뉴얼 열기
사용자 설명서 (RH80532GC029512)차례Legal - Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel'...2Legal - Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage an...2Legal - Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms...2Legal - Intel may make changes to specifications and product descriptions at any time, without notice.2Legal - Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incomp...2Legal - The Mobile Intel Pentium 4 Processor-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.2Legal - Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.2Legal - Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s Website at http://www.intel.com2Legal - Copyright © Intel Corporation 2000-2003.2Legal - Intel, Pentium, Intel NetBurst, and SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries.2Legal - * Other brands and names are the property of their respective owners.202_TOCHead - Contents301_LevelTOC - 1. Introduction 9301_LevelTOC - 2. Electrical Specifications 13301_LevelTOC - 3. System Bus Signal Quality Specifications 51301_LevelTOC - 4. Package Mechanical Specifications 61301_LevelTOC - 5. Pin Listing and Signal Definitions 67301_LevelTOC - 6. Thermal Specifications and Design Considerations 89301_LevelTOC - 7. Configuration and Low Power Features 93401_LevelTOC - 8. Debug Tools Specifications 97401_LevelTOC -403_TOCHead - Figures503_TOCHead - Tables603_TOCHead - Revision History8Title - Mobile Intel‚ Pentium‚ 4 Processor-M1DocType - Datasheet1Date -1Date - June 20031Date -101_Level - 1. Introduction902_Level - 1.1 Terminology1102_Level - 1.2 References1106_Table - Table 1. References1101_Level - 2. Electrical Specifications1302_Level - 2.1 System Bus and GTLREF1302_Level - 2.2 Power and Ground Pins1302_Level - 2.3 Decoupling Guidelines1303_Level - 2.3.1 VCC Decoupling1403_Level - 2.3.2 System Bus AGTL+ Decoupling1403_Level - 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking1406_Table - Table 2. Core Frequency to System Bus Multipliers14TableNotes - NOTES:14TableStep1 - 1. Ratio is used for debug purposes only.14TableStepn - 2. Listed frequencies are not necessarily committed production frequencies.1502_Level - 2.4 Voltage Identification and Power Sequencing1505_Figure - Figure 1. VCCVID Pin Voltage and Current Requirements1506_Table - Table 3. Voltage Identification Definition1603_Level - 2.4.1 Enhanced Intel® SpeedStep® Technology1603_Level - 2.4.2 Phase Lock Loop (PLL) Power and Filter1705_Figure - Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution17Footnote - .1805_Figure - Figure 3. Phase Lock Loop (PLL) Filter Requirements18TableNotes - NOTES:18TableStep1 - 1. Diagram not to scale.18TableStep1 - 2. No specification for frequencies beyond fcore (core frequency).18TableStep1 - 3. fpeak, if existent, should be less than 0.05 MHz.1803_Level - 2.4.3 Catastrophic Thermal Protection1802_Level - 2.5 Signal Terminations, Unused Pins and TESTHI[10:0]18Step1 - 1. TESTHI[1:0]19Stepn - 2. TESTHI[5:2]19Stepn - 3. TESTHI[10:8]1902_Level - 2.6 System Bus Signal Groups2006_Table - Table 4. System Bus Pin Groups21TableNotes - NOTES:21TableStep1 - 1. Refer to Section 5.2 for signal descriptions.21TableStepn - 2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements.21TableStepn - 3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.21TableStepn - 4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must be terminated on the system board. Refer to Section 2.5 and the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845...21TableStepn - 5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 7.1 for details.2102_Level - 2.7 Asynchronous GTL+ Signals2202_Level - 2.8 Test Access Port (TAP) Connection2202_Level - 2.9 System Bus Frequency Select Signals (BSEL[1:0])2206_Table - Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]2202_Level - 2.10 Maximum Ratings2306_Table - Table 6. Processor DC Absolute Maximum Ratings23TableNotes - NOTES:23TableStep1 - 1. This rating applies to any processor pin.23TableStepn - 2. Contact Intel for storage requirements in excess of one year.2302_Level - 2.11 Processor DC Specifications2306_Table - Table 7. Voltage and Current Specifications24TableNotes - NOTES:24TableStep1 - 1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements available at the time of publication.24TableStepn - 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 and Table 3 for more information. The VID bits will set the typical VCC with...24TableStepn - 3. The voltage specification requirements are measured at the system board socket ball with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MW minimum impedance. The maximum length of ground wire on the ...24TableStepn - 4. Refer to Table 8 to Table 11 and Figure 4 to Figure 6 for the minimum, typical, and maximum VCC (measured at the system board socket ball) allowed for a given current. The processor should not be subjected to any VCC and ICC c...24TableStepn - 5. VCC_MIN is defined at ICC_MAX.24TableStepn - 6. The current specified is also for AutoHALT State.24TableStepn - 7. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification shown in Table 8 to Table 11.24TableStepn - 8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor.24TableStepn - 9. Maximum specifications for ICC Core, ICC Stop-Grant, ICC Sleep, and ICC Deep Sleep are specified at VCC Static Max. derived from the tolerances in Table 8 through Table 11, TJ Max., and under maximum signal loading conditions.24TableStepn - 10. The specification is defined per PLL pin.25TableStepn - 11. The voltage response to a processor current load step (transient) must stay within the Transient Voltage Tolerance Window. The voltage surge or droop response measured in this window is typically on the order of several hundr...25TableStepn - 12. This specification applies to both static and transient components. The rising edge of VCCVID must be monotonic from 0 to 1.1 V. See Figure 1 for current requirements. In this case, monotonic is defined as continuously increa...2506_Table - Table 8. IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode)2505_Figure - Figure 4. Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)2606_Table - Table 9. IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery Optimized Mode)2705_Figure - Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)2806_Table - Table 10. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum Performance Mode (VID = 1.30 V, VID Offset = 4.62%)2806_Table - Table 11. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode (VID = 1.20 V, VID Offset = 4.62%)2905_Figure - Figure 6. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V)2906_Table - Table 12. System Bus Differential BCLK Specifications30TableNotes - NOTES:30TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.30TableStepn - 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.30TableStepn - 3. VHavg is the statistical average of the VH measured by the oscilloscope .30TableStepn - 4. Overshoot is defined as the absolute value of the maximum voltage.30TableStepn - 5. Undershoot is defined as the absolute value of the minimum voltage.30TableStepn - 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback.30TableStepn - 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis.30TableStepn - 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.30TableStepn - 9. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.30TableStepn - 10. DVCROSS is defined as the total variation of all crossing voltages as defined in note 2.3006_Table - Table 13. AGTL+ Signal Group DC Specifications31TableNotes - NOTES:31TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.31TableStepn - 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.31TableStepn - 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.31TableStepn - 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3.31TableStepn - 5. Refer to processor I/O Buffer Models for I/V characteristics.31TableStepn - 6. The VCC referred to in these specifications is the instantaneous VCC.31TableStepn - 7. Vol max of 0.450 Volts is guaranteed when driving into a test load of 50 W as indicated in Figure 8.31TableStepn - 8. Leakage to VSS with pin held at VCC.31TableStepn - 9. Leakage to VCC with pin held at 300 mV.3106_Table - Table 14. Asynchronous GTL+ Signal Group DC Specifications32TableNotes - NOTES:32TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.32TableStepn - 2. All outputs are open-drain.32TableStepn - 3. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3.32TableStepn - 4. The VCC referred to in these specifications refers to instantaneous VCC.32TableStepn - 5. This specification applies to the asynchronous GTL+ signal group.32TableStepn - 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in Figure 8.32TableStepn - 7. Refer to the processor I/O Buffer Models for I/V characteristics.32TableStepn - 8. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50 W as indicated in Figure 8 for the Asynchronous GTL+ signals.32TableStepn - 9. Leakage to VSS with pin held at VCC.32TableStepn - 10. Leakage to VCC with pin held at 300 mV.3206_Table - Table 15. PWRGOOD and TAP Signal Group DC Specifications33TableNotes - NOTES:33TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.33TableStepn - 2. All outputs are open-drain.33TableStepn - 3. TAP signal group must comply with the signal quality specifications in Section 3.33TableStepn - 4. Refer to I/O Buffer Models for I/V characteristics.33TableStepn - 5. The VCC referred to in these specifications refers to instantaneous VCC.33TableStepn - 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown if Figure 8.33TableStepn - 7. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50 Ohms as indicated in Figure 8 for the TAP Signals.33TableStepn - 8. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc for all TAP inputs.33TableStepn - 9. Leakage to VSS with pin held at VCC.33TableStepn - 10. Leakage to VCC with pin held at 300 mV.3306_Table - Table 16. ITPCLKOUT[1:0] DC Specifications33TableNotes - NOTES:33TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.33TableStepn - 2. These parameters are not tested and are based on design simulations.33TableStepn - 3. See Figure 7 for ITPCLKOUT[1:0] output buffer diagram.3305_Figure - Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram34TableNotes - NOTES:34TableStep1 - 1. See Table 16 for range of Ron.34TableStepn - 2. The Vcc referred to in this figure is the instantaneous Vcc.34TableStepn - 3. Refer to the appropriate platform design guidelines for the value of Rext.3406_Table - Table 17. BSEL [1:0] and VID[4:0] DC Specifications34TableNotes - NOTES:34TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.34TableStepn - 2. These parameters are not tested and are based on design simulations.34TableStepn - 3. Leakage to Vss with pin held at 2.50 V.3402_Level - 2.12 AGTL+ System Bus Specifications3406_Table - Table 18. AGTL+ Bus Voltage Definitions35TableNotes - NOTES:35TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.35TableStep1 - 2. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of VCC.35TableStep1 - 3. GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors or 1% tolerance matched resistors. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for i...35TableStep1 - 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O buffer models for I/V characteristics.35TableStep1 - 5. COMP resistance must be provided on the system board with 1% tolerance resistors. See the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for implementation details.35TableStep1 - 6. The VCC referred to in these specifications is the instantaneous VCC.3502_Level - 2.13 System Bus AC Specifications3506_Table - Table 19. System Bus Differential Clock Specifications36TableNotes - NOTES:36TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.36TableStep1 - 2. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2).36TableStep1 - 3. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability.36TableStep1 - 4. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).3606_Table - Table 20. System Bus Common Clock AC Specifications36TableNotes - NOTES:36TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.36TableStep1 - 2. Not 100% tested. Specified by design characterization.36TableStep1 - 3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.36TableStep1 - 4. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC ± 2%.36TableStep1 - 5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.4 V/ns to 4.0 V/ns.36TableStep1 - 6. RESET# can be asserted asynchronously, but must be deasserted synchronously.36TableStep1 - 7. This should be measured after VCC and BCLK[1:0] become stable.36TableStep1 - 8. Maximum specification applies only while PWRGOOD is asserted.3606_Table - Table 21. System Bus Source Synch AC Specifications AGTL+ Signal Group37TableNotes - NOTES:37TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.37TableStepn - 2. Not 100% tested. Specified by design characterization.37TableStepn - 3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are ...37TableStepn - 4. Unless otherwise noted these specifications apply to both data and address timings.37TableStepn - 5. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC ± 2%.37TableStepn - 6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.3 V/ns to 4.0V /ns.37TableStepn - 7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe.37TableStepn - 8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for more information on...37TableStepn - 9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for more information on ...37TableStepn - 10. The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of ADSTB#.37TableStepn - 11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.37TableStepn - 12. The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK period (...37TableStepn - 13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.3706_Table - Table 22. Miscellaneous Signals AC Specifications38TableNotes - NOTES:38TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.38TableStepn - 2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge at 0.5*VCC38TableStepn - 3. These signals may be driven asynchronously.38TableStepn - 4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.38TableStepn - 5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion and before the deassertion of PROCHOT# for the processor to complete current instruction execution. This spe...38TableStepn - 6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.3806_Table - Table 23. System Bus AC Specifications (Reset Conditions)38TableNotes - NOTES:38TableStep1 - 1. Before the deassertion of RESET#.38TableStepn - 2. After clock that deasserts RESET#.3806_Table - Table 24. TAP Signals AC Specifications39TableNotes - NOTES:39TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.39TableStepn - 2. Not 100% tested. Specified by design characterization.39TableStepn - 3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins.39TableStepn - 4. Rise and fall times are measured from the 20% to 80% points of the signal swing.39TableStepn - 5. Referenced to the rising edge of TCK.39TableStepn - 6. Referenced to the falling edge of TCK.39TableStepn - 7. Specifications for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of 0.5 V/ns39TableStepn - 8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.39TableStepn - 9. It is recommended that TMS be asserted while TRST# is being deasserted.3906_Table - Table 25. ITPCLKOUT[1:0] AC Specifications39TableNotes - NOTES:39TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.39TableStepn - 2. These parameters are not tested and are based on design simulations.39TableStepn - 3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.3906_Table - Table 26. Stop Grant/Sleep/Deep Sleep/Enhanced Intel SpeedStep Technology AC Specifications40TableNotes - NOTES:40TableStep1 - 1. Input signals other than RESET# must be held constant in the Sleep state.40TableStep1 - 2. The BCLK can be stopped after DPSLP# is asserted. The BCLK must be turned on and within specification before DPSLP# is deasserted.4002_Level - 2.14 Processor AC Timing Waveforms40TableNotes - NOTES:40TableStep1 - 1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.40TableStep1 - 2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Sou...40TableStep1 - 3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+ strobe signal timings are referenced at GTLREF at the processor core silicon.40TableStep1 - 4. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.5*VCC at the processor pins.4005_Figure - Figure 8. AC Test Circuit4105_Figure - Figure 9. TCK Clock Waveform4105_Figure - Figure 10. Differential Clock Waveform4205_Figure - Figure 11. Differential Clock Crosspoint Specification4305_Figure - Figure 12. System Bus Common Clock Valid Delay Timings4305_Figure - Figure 13. System Bus Reset and Configuration Timings4405_Figure - Figure 14. Source Synchronous 2X (Address) Timings4405_Figure - Figure 15. Source Synchronous 4X Timings4505_Figure - Figure 16. Power Up Sequence4605_Figure - Figure 17. Power Down Sequence4605_Figure - Figure 18. Test Reset Timings4705_Figure - Figure 19. THERMTRIP# to Vcc Timing4705_Figure - Figure 20. FERR#/PBE# Valid Delay Timing4705_Figure - Figure 21. TAP Valid Delay Timing4805_Figure - Figure 22. ITPCLKOUT Valid Delay Timing4805_Figure - Figure 23. Stop Grant/Sleep/Deep Sleep Timing4905_Figure - Figure 24. Enhanced Intel SpeedStep Technology/Deep Sleep Timing5001_Level - 3. System Bus Signal Quality Specifications5102_Level - 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines5106_Table - Table 27. BCLK Signal Quality Specifications51TableNotes - NOTES:51TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.51TableStep1 - 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specific...5105_Figure - Figure 25. BCLK Signal Integrity Waveform5202_Level - 3.2 System Bus Signal Quality Specifications and Measurement Guidelines5206_Table - Table 28. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups52TableNotes - NOTES:52TableStep1 - 1. All signal integrity specifications are measured at the processor silicon (pads).52TableStep1 - 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.52TableStep1 - 3. Specifications are for the edge rate of 0.3 - 4.0 V/ns.52TableStep1 - 4. All values specified by design characterization.52TableStep1 - 5. Please see Section 3.3 for maximum allowable overshoot.52TableStep1 - 6. Ringback between GTLREF + 10% and GTLREF - 10% is not supported.52TableStep1 - 7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other sources of system noise.5206_Table - Table 29. Ringback Specifications for PWRGOOD Input and TAP Signal Groups53TableNotes - NOTES:53TableStep1 - 1. All signal integrity specifications are measured at the processor silicon.53TableStepn - 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.53TableStepn - 3. Please see Section 3.3 for maximum allowable overshoot.53TableStepn - 4. Please see Section 2.11 for the DC specifications.5305_Figure - Figure 26. Low-to-High System Bus Receiver Ringback Tolerance5305_Figure - Figure 27. High-to-Low System Bus Receiver Ringback Tolerance5305_Figure - Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers5405_Figure - Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers5402_Level - 3.3 System Bus Signal Quality Specifications and Measurement Guidelines5503_Level - 3.3.1 Overshoot/Undershoot Guidelines5503_Level - 3.3.2 Overshoot/Undershoot Magnitude5503_Level - 3.3.3 Overshoot/Undershoot Pulse Duration55Note - Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration.5603_Level - 3.3.4 Activity Factor56Note - Note: 1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency.56Note - Note: 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#.56Note - Note: 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#.5603_Level - 3.3.5 Reading Overshoot/Undershoot Specification Tables56Step1 - 1. Determine the signal group a particular signal falls into. If the signal is an AGTL+ signal operating in the common clock domain, use Table 32. For AGTL+ signals operating in the 2x source synchronous domain, use Table 31. For AGTL...56Stepn - 2. Determine the magnitude of the overshoot (relative to VSS).56Stepn - 3. Determine the activity factor (how often does this overshoot occur?)56Stepn - 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed.56Stepn - 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications.5603_Level - 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications57Step1 - 1. Ensure no signal ever exceeds VCC or -0.25 V OR57Stepn - 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables OR57Stepn - 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst case overshoot or undershoot events...57TableNotes - NOTES:57TableStep1 - 1. Absolute Maximum Overshoot magnitude of 1.70 V must never be exceeded.57TableStepn - 2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative to VCC.57TableStepn - 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS.57TableStepn - 4. Ringback below VCC can not be subtracted from overshoots/undershoots.57TableStepn - 5. Lesser undershoot does not allocate longer or larger overshoot.57TableStepn - 6. OEM's are strongly encouraged to follow Intel provided layout guidelines.57TableStepn - 7. All values specified by design characterization.5706_Table - Table 30. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance57TableNotes - NOTES:57TableStep1 - 1. These specifications are measured at the processor core silicon.57TableStepn - 2. BCLK period is 10 ns.5706_Table - Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance58TableNotes - NOTES:58TableStep1 - 1. These specifications are measured at the processor core silicon.58TableStepn - 2. BCLK period is 10 ns.5806_Table - Table 32. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance58TableNotes - NOTES:58TableStep1 - 1. These specifications are measured at the processor core silicon.58TableStepn - 2. BCLK period is 10 ns.5806_Table - Table 33. Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/ Undershoot Tolerance59TableNotes - NOTES:59TableStep1 - 1. These specifications are measured at the processor core silicon.59TableStepn - 2. BCLK period is 10 ns.5905_Figure - Figure 30. Maximum Acceptable Overshoot/Undershoot Waveform5901_Level - 4. Package Mechanical Specifications6105_Figure - Figure 31. Micro-FCPGA Package Top and Bottom Isometric Views6105_Figure - Figure 32. Micro-FCPGA Package Top and Side View6206_Table - Table 34. Micro-FCPGA Package Dimensions63TableNotes - NOTES:63TableStep1 - 1. All Dimensions are subject to change. Values shown are for reference only.63TableStep1 - 2. Overall height with socket is based on design dimensions of the Micro-FCPGA package and socket with no thermal solution attached. Values were based on design specifications and tolerances. This dimension is subject to change b...6305_Figure - Figure 33. Micro-FCPGA Package - Bottom View6402_Level - 4.1 Processor Pin-Out6405_Figure - Figure 34. The Coordinates of the Processor Pins as Viewed From the Top of the Package.6506_Table - Table 35. Pin Listing by Pin Name6806_Table - Table 36. Pin Listing by Pin Number7401_Level - 5. Pin Listing and Signal Definitions6702_Level - 5.1 Mobile Intel Pentium 4 Processor-M Pin Assignments6702_Level - 5.2 Alphabetical Signals Reference8106_Table - Table 37. Signal Description (Page 8 of 8)8101_Level - 6. Thermal Specifications and Design Considerations8906_Table - Table 38. Power Specifications for the Mobile Intel Pentium 4 Processor-M89TableNotes - NOTES:89TableStep1 - 1. TDP is defined as the worst case power dissipated by the processor while executing publicly available software under normal operating conditions at nominal voltages that meet the load line specifications. The TDP number shown ...89TableStep1 - 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated.90TableStep1 - 3. The maximum junction temperature (TJ) is specified as the hottest location on the die. The thermal monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 6.1.1 for TJ measurement gu...9002_Level - 6.1 Thermal Specifications9003_Level - 6.1.1 Thermal Diode90Note - Note: The reading of the thermal sensor connected to the thermal diode does not reflect the temperature of the hottest location on the die (TJ). This is due to inaccuracies in the thermal diode, on-die temperature gradients between the...9006_Table - Table 39. Thermal Diode Interface9006_Table - Table 40. Thermal Diode Specifications90TableNotes - NOTES:90TableStep1 - 1. Intel does not support or recommend operation of the thermal diode under reverse bias.90TableStepn - 2. Characterized at 100 C.90TableStepn - 3. Not 100% tested. Specified by design characterization.90TableStepn - 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVd/nkT) -1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = ...90TableStepn - 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resi...9103_Level - 6.1.2 Thermal Monitor9101_Level - 7. Configuration and Low Power Features9302_Level - 7.1 Power-On Configuration Options9306_Table - Table 41. Power-On Configuration Option Pins9302_Level - 7.2 Clock Control and Low Power States9303_Level - 7.2.1 Normal State9303_Level - 7.2.2 AutoHALT Powerdown State9305_Figure - Figure 35. Clock Control States9403_Level - 7.2.3 Stop-Grant State9403_Level - 7.2.4 HALT/Grant Snoop State9503_Level - 7.2.5 Sleep State9503_Level - 7.2.6 Deep Sleep State9503_Level - 7.2.7 Deeper Sleep State9602_Level - 7.3 Enhanced Intel SpeedStep Technology9601_Level - 8. Debug Tools Specifications9702_Level - 8.1 Logic Analyzer Interface (LAI)9703_Level - 8.1.1 Mechanical Considerations9703_Level - 8.1.2 Electrical Considerations9701_LevelTOC - 1. Introduction 901_LevelTOC - 2. Electrical Specifications 1301_LevelTOC - 3. System Bus Signal Quality Specifications 5101_LevelTOC - 4. Package Mechanical Specifications 6101_LevelTOC - 5. Pin Listing and Signal Definitions 6701_LevelTOC - 6. Thermal Specifications and Design Considerations 8901_LevelTOC - 7. Configuration and Low Power Features 9301_LevelTOC - 8. Debug Tools Specifications 97크기: 5.19메가바이트페이지: 97Language: English매뉴얼 열기
사용자 설명서 (RH80532GC033512)차례Legal - Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel'...2Legal - Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage an...2Legal - Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms...2Legal - Intel may make changes to specifications and product descriptions at any time, without notice.2Legal - Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incomp...2Legal - The Mobile Intel Pentium 4 Processor-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.2Legal - Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.2Legal - Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s Website at http://www.intel.com2Legal - Copyright © Intel Corporation 2000-2003.2Legal - Intel, Pentium, Intel NetBurst, and SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries.2Legal - * Other brands and names are the property of their respective owners.202_TOCHead - Contents301_LevelTOC - 1. Introduction 9301_LevelTOC - 2. Electrical Specifications 13301_LevelTOC - 3. System Bus Signal Quality Specifications 51301_LevelTOC - 4. Package Mechanical Specifications 61301_LevelTOC - 5. Pin Listing and Signal Definitions 67301_LevelTOC - 6. Thermal Specifications and Design Considerations 89301_LevelTOC - 7. Configuration and Low Power Features 93401_LevelTOC - 8. Debug Tools Specifications 97401_LevelTOC -403_TOCHead - Figures503_TOCHead - Tables603_TOCHead - Revision History8Title - Mobile Intel‚ Pentium‚ 4 Processor-M1DocType - Datasheet1Date -1Date - June 20031Date -101_Level - 1. Introduction902_Level - 1.1 Terminology1102_Level - 1.2 References1106_Table - Table 1. References1101_Level - 2. Electrical Specifications1302_Level - 2.1 System Bus and GTLREF1302_Level - 2.2 Power and Ground Pins1302_Level - 2.3 Decoupling Guidelines1303_Level - 2.3.1 VCC Decoupling1403_Level - 2.3.2 System Bus AGTL+ Decoupling1403_Level - 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking1406_Table - Table 2. Core Frequency to System Bus Multipliers14TableNotes - NOTES:14TableStep1 - 1. Ratio is used for debug purposes only.14TableStepn - 2. Listed frequencies are not necessarily committed production frequencies.1502_Level - 2.4 Voltage Identification and Power Sequencing1505_Figure - Figure 1. VCCVID Pin Voltage and Current Requirements1506_Table - Table 3. Voltage Identification Definition1603_Level - 2.4.1 Enhanced Intel® SpeedStep® Technology1603_Level - 2.4.2 Phase Lock Loop (PLL) Power and Filter1705_Figure - Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution17Footnote - .1805_Figure - Figure 3. Phase Lock Loop (PLL) Filter Requirements18TableNotes - NOTES:18TableStep1 - 1. Diagram not to scale.18TableStep1 - 2. No specification for frequencies beyond fcore (core frequency).18TableStep1 - 3. fpeak, if existent, should be less than 0.05 MHz.1803_Level - 2.4.3 Catastrophic Thermal Protection1802_Level - 2.5 Signal Terminations, Unused Pins and TESTHI[10:0]18Step1 - 1. TESTHI[1:0]19Stepn - 2. TESTHI[5:2]19Stepn - 3. TESTHI[10:8]1902_Level - 2.6 System Bus Signal Groups2006_Table - Table 4. System Bus Pin Groups21TableNotes - NOTES:21TableStep1 - 1. Refer to Section 5.2 for signal descriptions.21TableStepn - 2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements.21TableStepn - 3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.21TableStepn - 4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must be terminated on the system board. Refer to Section 2.5 and the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845...21TableStepn - 5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 7.1 for details.2102_Level - 2.7 Asynchronous GTL+ Signals2202_Level - 2.8 Test Access Port (TAP) Connection2202_Level - 2.9 System Bus Frequency Select Signals (BSEL[1:0])2206_Table - Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]2202_Level - 2.10 Maximum Ratings2306_Table - Table 6. Processor DC Absolute Maximum Ratings23TableNotes - NOTES:23TableStep1 - 1. This rating applies to any processor pin.23TableStepn - 2. Contact Intel for storage requirements in excess of one year.2302_Level - 2.11 Processor DC Specifications2306_Table - Table 7. Voltage and Current Specifications24TableNotes - NOTES:24TableStep1 - 1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements available at the time of publication.24TableStepn - 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 and Table 3 for more information. The VID bits will set the typical VCC with...24TableStepn - 3. The voltage specification requirements are measured at the system board socket ball with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MW minimum impedance. The maximum length of ground wire on the ...24TableStepn - 4. Refer to Table 8 to Table 11 and Figure 4 to Figure 6 for the minimum, typical, and maximum VCC (measured at the system board socket ball) allowed for a given current. The processor should not be subjected to any VCC and ICC c...24TableStepn - 5. VCC_MIN is defined at ICC_MAX.24TableStepn - 6. The current specified is also for AutoHALT State.24TableStepn - 7. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification shown in Table 8 to Table 11.24TableStepn - 8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor.24TableStepn - 9. Maximum specifications for ICC Core, ICC Stop-Grant, ICC Sleep, and ICC Deep Sleep are specified at VCC Static Max. derived from the tolerances in Table 8 through Table 11, TJ Max., and under maximum signal loading conditions.24TableStepn - 10. The specification is defined per PLL pin.25TableStepn - 11. The voltage response to a processor current load step (transient) must stay within the Transient Voltage Tolerance Window. The voltage surge or droop response measured in this window is typically on the order of several hundr...25TableStepn - 12. This specification applies to both static and transient components. The rising edge of VCCVID must be monotonic from 0 to 1.1 V. See Figure 1 for current requirements. In this case, monotonic is defined as continuously increa...2506_Table - Table 8. IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum Performance Mode)2505_Figure - Figure 4. Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)2606_Table - Table 9. IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery Optimized Mode)2705_Figure - Figure 5. Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)2806_Table - Table 10. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum Performance Mode (VID = 1.30 V, VID Offset = 4.62%)2806_Table - Table 11. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode (VID = 1.20 V, VID Offset = 4.62%)2905_Figure - Figure 6. Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting = 1.30 V)2906_Table - Table 12. System Bus Differential BCLK Specifications30TableNotes - NOTES:30TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.30TableStepn - 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1.30TableStepn - 3. VHavg is the statistical average of the VH measured by the oscilloscope .30TableStepn - 4. Overshoot is defined as the absolute value of the maximum voltage.30TableStepn - 5. Undershoot is defined as the absolute value of the minimum voltage.30TableStepn - 6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback.30TableStepn - 7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis.30TableStepn - 8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.30TableStepn - 9. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.30TableStepn - 10. DVCROSS is defined as the total variation of all crossing voltages as defined in note 2.3006_Table - Table 13. AGTL+ Signal Group DC Specifications31TableNotes - NOTES:31TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.31TableStepn - 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.31TableStepn - 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.31TableStepn - 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3.31TableStepn - 5. Refer to processor I/O Buffer Models for I/V characteristics.31TableStepn - 6. The VCC referred to in these specifications is the instantaneous VCC.31TableStepn - 7. Vol max of 0.450 Volts is guaranteed when driving into a test load of 50 W as indicated in Figure 8.31TableStepn - 8. Leakage to VSS with pin held at VCC.31TableStepn - 9. Leakage to VCC with pin held at 300 mV.3106_Table - Table 14. Asynchronous GTL+ Signal Group DC Specifications32TableNotes - NOTES:32TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.32TableStepn - 2. All outputs are open-drain.32TableStepn - 3. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Section 3.32TableStepn - 4. The VCC referred to in these specifications refers to instantaneous VCC.32TableStepn - 5. This specification applies to the asynchronous GTL+ signal group.32TableStepn - 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in Figure 8.32TableStepn - 7. Refer to the processor I/O Buffer Models for I/V characteristics.32TableStepn - 8. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50 W as indicated in Figure 8 for the Asynchronous GTL+ signals.32TableStepn - 9. Leakage to VSS with pin held at VCC.32TableStepn - 10. Leakage to VCC with pin held at 300 mV.3206_Table - Table 15. PWRGOOD and TAP Signal Group DC Specifications33TableNotes - NOTES:33TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.33TableStepn - 2. All outputs are open-drain.33TableStepn - 3. TAP signal group must comply with the signal quality specifications in Section 3.33TableStepn - 4. Refer to I/O Buffer Models for I/V characteristics.33TableStepn - 5. The VCC referred to in these specifications refers to instantaneous VCC.33TableStepn - 6. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown if Figure 8.33TableStepn - 7. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50 Ohms as indicated in Figure 8 for the TAP Signals.33TableStepn - 8. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc for all TAP inputs.33TableStepn - 9. Leakage to VSS with pin held at VCC.33TableStepn - 10. Leakage to VCC with pin held at 300 mV.3306_Table - Table 16. ITPCLKOUT[1:0] DC Specifications33TableNotes - NOTES:33TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.33TableStepn - 2. These parameters are not tested and are based on design simulations.33TableStepn - 3. See Figure 7 for ITPCLKOUT[1:0] output buffer diagram.3305_Figure - Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram34TableNotes - NOTES:34TableStep1 - 1. See Table 16 for range of Ron.34TableStepn - 2. The Vcc referred to in this figure is the instantaneous Vcc.34TableStepn - 3. Refer to the appropriate platform design guidelines for the value of Rext.3406_Table - Table 17. BSEL [1:0] and VID[4:0] DC Specifications34TableNotes - NOTES:34TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.34TableStepn - 2. These parameters are not tested and are based on design simulations.34TableStepn - 3. Leakage to Vss with pin held at 2.50 V.3402_Level - 2.12 AGTL+ System Bus Specifications3406_Table - Table 18. AGTL+ Bus Voltage Definitions35TableNotes - NOTES:35TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.35TableStep1 - 2. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of VCC.35TableStep1 - 3. GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors or 1% tolerance matched resistors. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for i...35TableStep1 - 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O buffer models for I/V characteristics.35TableStep1 - 5. COMP resistance must be provided on the system board with 1% tolerance resistors. See the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for implementation details.35TableStep1 - 6. The VCC referred to in these specifications is the instantaneous VCC.3502_Level - 2.13 System Bus AC Specifications3506_Table - Table 19. System Bus Differential Clock Specifications36TableNotes - NOTES:36TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.36TableStep1 - 2. The period specified here is the average period. A given period may vary from this specification as governed by the period stability specification (T2).36TableStep1 - 3. In this context, period stability is defined as the worst case timing difference between successive crossover voltages. In other words, the largest absolute difference between adjacent clock periods must be less than the period stability.36TableStep1 - 4. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).3606_Table - Table 20. System Bus Common Clock AC Specifications36TableNotes - NOTES:36TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.36TableStep1 - 2. Not 100% tested. Specified by design characterization.36TableStep1 - 3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.36TableStep1 - 4. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC ± 2%.36TableStep1 - 5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.4 V/ns to 4.0 V/ns.36TableStep1 - 6. RESET# can be asserted asynchronously, but must be deasserted synchronously.36TableStep1 - 7. This should be measured after VCC and BCLK[1:0] become stable.36TableStep1 - 8. Maximum specification applies only while PWRGOOD is asserted.3606_Table - Table 21. System Bus Source Synch AC Specifications AGTL+ Signal Group37TableNotes - NOTES:37TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.37TableStepn - 2. Not 100% tested. Specified by design characterization.37TableStepn - 3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Source synchronous address signals are ...37TableStepn - 4. Unless otherwise noted these specifications apply to both data and address timings.37TableStepn - 5. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF at 2/3 VCC ± 2%.37TableStepn - 6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 0.3 V/ns to 4.0V /ns.37TableStepn - 7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe.37TableStepn - 8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for more information on...37TableStepn - 9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the Mobile Intel‚ Pentium‚ 4 Processor-M and Intel‚ 845MP/845MZ Chipset Platform Design Guide for more information on ...37TableStepn - 10. The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of ADSTB#.37TableStepn - 11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.37TableStepn - 12. The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK period (...37TableStepn - 13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.3706_Table - Table 22. Miscellaneous Signals AC Specifications38TableNotes - NOTES:38TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.38TableStepn - 2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All Asynch GTL+ signal timings are referenced at GTLREF. PWRGOOD is referenced to the BCLK0 rising edge at 0.5*VCC38TableStepn - 3. These signals may be driven asynchronously.38TableStepn - 4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.38TableStepn - 5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion and before the deassertion of PROCHOT# for the processor to complete current instruction execution. This spe...38TableStepn - 6. See Section 7.2 for additional timing requirements for entering and leaving the low power states.3806_Table - Table 23. System Bus AC Specifications (Reset Conditions)38TableNotes - NOTES:38TableStep1 - 1. Before the deassertion of RESET#.38TableStepn - 2. After clock that deasserts RESET#.3806_Table - Table 24. TAP Signals AC Specifications39TableNotes - NOTES:39TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.39TableStepn - 2. Not 100% tested. Specified by design characterization.39TableStepn - 3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins.39TableStepn - 4. Rise and fall times are measured from the 20% to 80% points of the signal swing.39TableStepn - 5. Referenced to the rising edge of TCK.39TableStepn - 6. Referenced to the falling edge of TCK.39TableStepn - 7. Specifications for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of 0.5 V/ns39TableStepn - 8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.39TableStepn - 9. It is recommended that TMS be asserted while TRST# is being deasserted.3906_Table - Table 25. ITPCLKOUT[1:0] AC Specifications39TableNotes - NOTES:39TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.39TableStepn - 2. These parameters are not tested and are based on design simulations.39TableStepn - 3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.3906_Table - Table 26. Stop Grant/Sleep/Deep Sleep/Enhanced Intel SpeedStep Technology AC Specifications40TableNotes - NOTES:40TableStep1 - 1. Input signals other than RESET# must be held constant in the Sleep state.40TableStep1 - 2. The BCLK can be stopped after DPSLP# is asserted. The BCLK must be turned on and within specification before DPSLP# is deasserted.4002_Level - 2.14 Processor AC Timing Waveforms40TableNotes - NOTES:40TableStep1 - 1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the processor core.40TableStep1 - 2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the falling edge of their associated data strobe. Sou...40TableStep1 - 3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+ strobe signal timings are referenced at GTLREF at the processor core silicon.40TableStep1 - 4. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.5*VCC at the processor pins.4005_Figure - Figure 8. AC Test Circuit4105_Figure - Figure 9. TCK Clock Waveform4105_Figure - Figure 10. Differential Clock Waveform4205_Figure - Figure 11. Differential Clock Crosspoint Specification4305_Figure - Figure 12. System Bus Common Clock Valid Delay Timings4305_Figure - Figure 13. System Bus Reset and Configuration Timings4405_Figure - Figure 14. Source Synchronous 2X (Address) Timings4405_Figure - Figure 15. Source Synchronous 4X Timings4505_Figure - Figure 16. Power Up Sequence4605_Figure - Figure 17. Power Down Sequence4605_Figure - Figure 18. Test Reset Timings4705_Figure - Figure 19. THERMTRIP# to Vcc Timing4705_Figure - Figure 20. FERR#/PBE# Valid Delay Timing4705_Figure - Figure 21. TAP Valid Delay Timing4805_Figure - Figure 22. ITPCLKOUT Valid Delay Timing4805_Figure - Figure 23. Stop Grant/Sleep/Deep Sleep Timing4905_Figure - Figure 24. Enhanced Intel SpeedStep Technology/Deep Sleep Timing5001_Level - 3. System Bus Signal Quality Specifications5102_Level - 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines5106_Table - Table 27. BCLK Signal Quality Specifications51TableNotes - NOTES:51TableStep1 - 1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.51TableStep1 - 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specific...5105_Figure - Figure 25. BCLK Signal Integrity Waveform5202_Level - 3.2 System Bus Signal Quality Specifications and Measurement Guidelines5206_Table - Table 28. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups52TableNotes - NOTES:52TableStep1 - 1. All signal integrity specifications are measured at the processor silicon (pads).52TableStep1 - 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.52TableStep1 - 3. Specifications are for the edge rate of 0.3 - 4.0 V/ns.52TableStep1 - 4. All values specified by design characterization.52TableStep1 - 5. Please see Section 3.3 for maximum allowable overshoot.52TableStep1 - 6. Ringback between GTLREF + 10% and GTLREF - 10% is not supported.52TableStep1 - 7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other sources of system noise.5206_Table - Table 29. Ringback Specifications for PWRGOOD Input and TAP Signal Groups53TableNotes - NOTES:53TableStep1 - 1. All signal integrity specifications are measured at the processor silicon.53TableStepn - 2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M frequencies.53TableStepn - 3. Please see Section 3.3 for maximum allowable overshoot.53TableStepn - 4. Please see Section 2.11 for the DC specifications.5305_Figure - Figure 26. Low-to-High System Bus Receiver Ringback Tolerance5305_Figure - Figure 27. High-to-Low System Bus Receiver Ringback Tolerance5305_Figure - Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers5405_Figure - Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers5402_Level - 3.3 System Bus Signal Quality Specifications and Measurement Guidelines5503_Level - 3.3.1 Overshoot/Undershoot Guidelines5503_Level - 3.3.2 Overshoot/Undershoot Magnitude5503_Level - 3.3.3 Overshoot/Undershoot Pulse Duration55Note - Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration.5603_Level - 3.3.4 Activity Factor56Note - Note: 1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency.56Note - Note: 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#.56Note - Note: 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#.5603_Level - 3.3.5 Reading Overshoot/Undershoot Specification Tables56Step1 - 1. Determine the signal group a particular signal falls into. If the signal is an AGTL+ signal operating in the common clock domain, use Table 32. For AGTL+ signals operating in the 2x source synchronous domain, use Table 31. For AGTL...56Stepn - 2. Determine the magnitude of the overshoot (relative to VSS).56Stepn - 3. Determine the activity factor (how often does this overshoot occur?)56Stepn - 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed.56Stepn - 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications.5603_Level - 3.3.6 Conformance Determination to Overshoot/Undershoot Specifications57Step1 - 1. Ensure no signal ever exceeds VCC or -0.25 V OR57Stepn - 2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables OR57Stepn - 3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the AF = 1 specifications. If all of these worst case overshoot or undershoot events...57TableNotes - NOTES:57TableStep1 - 1. Absolute Maximum Overshoot magnitude of 1.70 V must never be exceeded.57TableStepn - 2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative to VCC.57TableStepn - 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS.57TableStepn - 4. Ringback below VCC can not be subtracted from overshoots/undershoots.57TableStepn - 5. Lesser undershoot does not allocate longer or larger overshoot.57TableStepn - 6. OEM's are strongly encouraged to follow Intel provided layout guidelines.57TableStepn - 7. All values specified by design characterization.5706_Table - Table 30. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance57TableNotes - NOTES:57TableStep1 - 1. These specifications are measured at the processor core silicon.57TableStepn - 2. BCLK period is 10 ns.5706_Table - Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance58TableNotes - NOTES:58TableStep1 - 1. These specifications are measured at the processor core silicon.58TableStepn - 2. BCLK period is 10 ns.5806_Table - Table 32. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance58TableNotes - NOTES:58TableStep1 - 1. These specifications are measured at the processor core silicon.58TableStepn - 2. BCLK period is 10 ns.5806_Table - Table 33. Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups Overshoot/ Undershoot Tolerance59TableNotes - NOTES:59TableStep1 - 1. These specifications are measured at the processor core silicon.59TableStepn - 2. BCLK period is 10 ns.5905_Figure - Figure 30. Maximum Acceptable Overshoot/Undershoot Waveform5901_Level - 4. Package Mechanical Specifications6105_Figure - Figure 31. Micro-FCPGA Package Top and Bottom Isometric Views6105_Figure - Figure 32. Micro-FCPGA Package Top and Side View6206_Table - Table 34. Micro-FCPGA Package Dimensions63TableNotes - NOTES:63TableStep1 - 1. All Dimensions are subject to change. Values shown are for reference only.63TableStep1 - 2. Overall height with socket is based on design dimensions of the Micro-FCPGA package and socket with no thermal solution attached. Values were based on design specifications and tolerances. This dimension is subject to change b...6305_Figure - Figure 33. Micro-FCPGA Package - Bottom View6402_Level - 4.1 Processor Pin-Out6405_Figure - Figure 34. The Coordinates of the Processor Pins as Viewed From the Top of the Package.6506_Table - Table 35. Pin Listing by Pin Name6806_Table - Table 36. Pin Listing by Pin Number7401_Level - 5. Pin Listing and Signal Definitions6702_Level - 5.1 Mobile Intel Pentium 4 Processor-M Pin Assignments6702_Level - 5.2 Alphabetical Signals Reference8106_Table - Table 37. Signal Description (Page 8 of 8)8101_Level - 6. Thermal Specifications and Design Considerations8906_Table - Table 38. Power Specifications for the Mobile Intel Pentium 4 Processor-M89TableNotes - NOTES:89TableStep1 - 1. TDP is defined as the worst case power dissipated by the processor while executing publicly available software under normal operating conditions at nominal voltages that meet the load line specifications. The TDP number shown ...89TableStep1 - 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated.90TableStep1 - 3. The maximum junction temperature (TJ) is specified as the hottest location on the die. The thermal monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 6.1.1 for TJ measurement gu...9002_Level - 6.1 Thermal Specifications9003_Level - 6.1.1 Thermal Diode90Note - Note: The reading of the thermal sensor connected to the thermal diode does not reflect the temperature of the hottest location on the die (TJ). This is due to inaccuracies in the thermal diode, on-die temperature gradients between the...9006_Table - Table 39. Thermal Diode Interface9006_Table - Table 40. Thermal Diode Specifications90TableNotes - NOTES:90TableStep1 - 1. Intel does not support or recommend operation of the thermal diode under reverse bias.90TableStepn - 2. Characterized at 100 C.90TableStepn - 3. Not 100% tested. Specified by design characterization.90TableStepn - 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVd/nkT) -1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = ...90TableStepn - 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resi...9103_Level - 6.1.2 Thermal Monitor9101_Level - 7. Configuration and Low Power Features9302_Level - 7.1 Power-On Configuration Options9306_Table - Table 41. Power-On Configuration Option Pins9302_Level - 7.2 Clock Control and Low Power States9303_Level - 7.2.1 Normal State9303_Level - 7.2.2 AutoHALT Powerdown State9305_Figure - Figure 35. Clock Control States9403_Level - 7.2.3 Stop-Grant State9403_Level - 7.2.4 HALT/Grant Snoop State9503_Level - 7.2.5 Sleep State9503_Level - 7.2.6 Deep Sleep State9503_Level - 7.2.7 Deeper Sleep State9602_Level - 7.3 Enhanced Intel SpeedStep Technology9601_Level - 8. Debug Tools Specifications9702_Level - 8.1 Logic Analyzer Interface (LAI)9703_Level - 8.1.1 Mechanical Considerations9703_Level - 8.1.2 Electrical Considerations9701_LevelTOC - 1. Introduction 901_LevelTOC - 2. Electrical Specifications 1301_LevelTOC - 3. System Bus Signal Quality Specifications 5101_LevelTOC - 4. Package Mechanical Specifications 6101_LevelTOC - 5. Pin Listing and Signal Definitions 6701_LevelTOC - 6. Thermal Specifications and Design Considerations 8901_LevelTOC - 7. Configuration and Low Power Features 9301_LevelTOC - 8. Debug Tools Specifications 97크기: 5.19메가바이트페이지: 97Language: English매뉴얼 열기
