사용자 설명서 (59P5107)차례Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz1Contents3Figures4Tables51.0 Introduction9Table 1. Features Comparison for Low Voltage Intel® Xeon™ Processors101.1 Terminology101.1.1 Processor Packaging Terminology101.2 State of Data111.3 References112.0 Electrical Specifications132.1 System Bus and GTLREF132.2 Power and Ground Pins132.3 Decoupling Guidelines132.3.1 VCC Decoupling142.3.2 System Bus AGTL+ Decoupling142.4 System Bus Clock (BCLK[1:0]) and Processor Clocking14Table 2. Front Side Bus-to-Core Frequency Ratio142.4.1 Bus Clock15Table 3. System Bus Clock Frequency Select Truth Table for BSEL[1:0]152.5 PLL Filter15Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution16Figure 2. Phase Lock Loop (PLL) Filter Requirements162.5.1 Mixing Processors172.6 Voltage Identification17Table 4. Voltage Identification Definition182.6.1 Mixing Processors of Different Voltages182.7 Reserved Or Unused Pins192.8 System Bus Signal Groups19Table 5. System Bus Signal Groups202.9 Asynchronous GTL+ Signals212.10 Maximum Ratings21Table 6. Processor Absolute Maximum Ratings212.11 Processor DC Specifications22Table 7. Voltage and Current Specifications23Figure 3. Low Voltage Intel® Xeon™ Processor Voltage and Current Projections in a Dual-Processor Configuration24Table 8. System Bus Differential BCLK Specifications (Sheet 1 of 2)24Table 9. AGTL+ Signal Group DC Specifications25Table 10. TAP and PWRGOOD Signal Group DC Specifications26Table 11. Asynchronous GTL+ Signal Group DC Specifications262.12 AGTL+ System Bus Specifications27Table 12. AGTL+ Bus Voltage Definitions272.13 System Bus AC Specifications27Table 13. System Bus Differential Clock Specifications28Table 14. System Bus Common Clock AC Specifications29Table 15. System Bus Source Synchronous AC Specifications (Sheet 1 of 2)29Table 16. Miscellaneous Signals+ AC Specifications30Table 17. System Bus AC Specifications (Reset Conditions)31Table 18. TAP Signal Group AC Specifications312.14 Processor AC Timing Waveforms31Figure 4. Electrical Test Circuit32Figure 5. TCK Clock Waveform32Figure 6. Differential Clock Waveform33Figure 7. Differential Clock Crosspoint Specification33Figure 8. System Bus Common Clock Valid Delay Timing Waveform34Figure 9. System Bus Source Synchronous 2X (Address) Timing Waveform34Figure 10. System Bus Source Synchronous 4X (Data) Timing Waveform35Figure 11. System Bus Reset and Configuration Timing Waveform36Figure 12. Power-On Reset and Configuration Timing Waveform36Figure 13. TAP Valid Delay Timing Waveform37Figure 14. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform37Figure 15. THERMTRIP# to VCC Timing37Figure 16. Example 3.3 VDC/VID_VCC Sequencing383.0 System Bus Signal Quality Specifications393.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines39Table 19. BCLK Signal Quality Specifications39Figure 17. BCLK[1:0] Signal Integrity Waveform403.2 System Bus Signal Quality Specifications and Measurement Guidelines40Table 20. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers40Table 21. Ringback Specifications for TAP Buffers41Figure 18. Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers41Figure 19. High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+ Buffers41Figure 20. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers42Figure 21. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffer433.3 System Bus Signal Quality Specifications and Measurement Guidelines433.3.1 Overshoot/Undershoot Guidelines433.3.2 Overshoot/Undershoot Magnitude443.3.3 Overshoot/Undershoot Pulse Duration443.3.4 Activity Factor443.3.5 Reading Overshoot/Undershoot Specification Tables453.3.6 Determining When a System Meets the Overshoot/Undershoot Specifications45Table 22. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance46Table 23. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance46Table 24. Common Clock (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance47Table 25. 400 MHz Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/Undershoot Tolerance (Sheet 1 of 2)47Table 26. Source Synchronous (533 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance48Table 27. Source Synchronous (533 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (Sheet 1 of 2)48Table 28. Common Clock (533 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance49Table 29. 533 MHz Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/ Undershoot Tolerance49Figure 22. Maximum Acceptable Overshoot/Undershoot Waveform504.0 Mechanical Specifications51Figure 23. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Assembly Drawing514.1 Mechanical Specifications52Figure 24. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Top View-Component Placement Detail52Figure 25. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Drawing53Table 30. Dimensions for the Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package54Figure 26. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Top View-Component Height Keep-In54Figure 27. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Cross Section View, Pin Side Component Keep-In55Figure 28. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Pin Detail55Figure 29. Low Voltage Intel® Xeon™ Processor FC-µPGA2 Package: IHS Flatness and Tilt Drawing564.2 Processor Package Load Specifications56Table 31. Package Dynamic and Static Load Specifications564.3 Insertion Specifications574.4 Mass Specifications57Table 32. Processor Mass574.5 Materials57Table 33. Processor Material Properties574.6 Markings58Figure 30. Processor Top-Side Markings58Figure 31. Processor Bottom-Side Markings584.7 Processor Pin-Out Diagram58Figure 32. Processor Pin Out Diagram: Top View59Figure 33. Processor Pin Out Diagram: Bottom View605.0 Pin Listing and Signal Definitions615.1 Processor Pin Assignments615.1.1 Pin Listing by Pin Name61Table 34. Pin Listing by Pin Name615.1.2 Pin Listing by Pin Number70Table 35. Pin Listing by Pin Number705.2 Signal Definitions79Table 36. Signal Definitions (Sheet 1 of 9)796.0 Thermal Specifications89Figure 34. Processor with Thermal and Mechanical Components - Exploded View896.1 Thermal Specifications89Table 37. Processor Thermal Design Power906.2 Measurements for Thermal Specifications906.2.1 Processor Case Temperature Measurement90Figure 35. Thermal Measurement Point for Processor TCASE917.0 Features937.1 Power-On Configuration Options93Table 38. Power-On Configuration Option Pins937.2 Clock Control and Low Power States937.2.1 Normal State-State 1937.2.2 AutoHALT Powerdown State-State 293Figure 36. Stop Clock State Machine947.2.3 Stop-Grant State-State 3947.2.4 HALT/Grant Snoop State-State 4957.2.5 Sleep State-State 5957.2.6 Bus Response During Low Power States967.3 Thermal Monitor967.3.1 Thermal Diode967.4 Thermal Diode97Table 39. Thermal Diode Parameters97Table 40. Thermal Diode Interface978.0 Debug Tools Specifications998.1 Logic Analyzer Interface (LAI)998.1.1 Mechanical Considerations998.1.2 Electrical Considerations999.0 Appendix A1019.1 Processor Core Frequency Determination101크기: 2.29메가바이트페이지: 102Language: English매뉴얼 열기